For full testing it is advised to get a controller that can handle 4-wire SPI in mode 0. There are four pins that need to be accessed at a minimum for SPI on the TCAN284XEVM. These are SDO (serial data out), SDI (serial data in), SCK (Serial Clock), and nCS (active low chip select) this pins can be accessed through header block J29. To connect the EVM to a 4-wire SPI capable controller, SDO should connect to the controllers data input pin. SDI should connect to controllers data output pin. SCK should connect to SPI clock on controller. The suggestion is that a minimum of 1MHz is used for SPI speed, and nCS is connected to nCS. The TCAN284XX and TCAN285XX devices are by default in mode 0 for SPI. Meaning the clock polarity is default low, and data is sampled on the rising edge and shifted on the falling edge. The user can change the device to SPI modes 1, 2, or 3, but the initial configuration must be done in mode 0. By default, the TCAN284XX and TCAN285XX devices are in one byte transaction mode with no CRC. Meaning there are 16 clock pulses per SPI transaction. For read commands, both SDO and SDI act a bit differently. The SDI pin should be given a 7 bit address and a 0 bit to indicate a read followed by nothing else for the rest of the transaction. SDO immediately starts outputting the 8-bit global interrupt vector. The address is simultaneously sent to SDI pin. After the global interrupt data has been transmitted out of the SDO pin, the request register data follows. Data is transmitted MSB.

Figure 3-1 SPI Read - One Byte Mode

Figure 3-2 SPI Write - One Byte Mode

To verify a valid SPI connection there are two tests to perform, an ID validation test and a SPI Scratch Pad test. For prototyping and debugging purposes, the suggestion is holding SW high to prevent the watchdog from putting the device to sleep when prototyping. After the board powers up and reaches standby mode, the SPI tests can commence. The first test is reading the ID registers of the specific TCAN284XX/TCAN285XX device on board. There are 8 ID registers on these devices starting at address 0h and going through address 7h. The registers are read only so the data is constant and always known. For example, if validating the TCAN28475 the 8 registers reads back 0x54, 0x43, 0x41, 0x32, 0x38, 0x34, 0x37, 0x35 from ID registers 0h through 7h. For specific device ID, please see DEVICE_ID_y register table in respective devices data sheet. If the ID is valid after read, two things have been confirmed: SPI Read works and device is giving expected ID. The next test checks both the SPI read and write capabilities by using the Scratch_Pad_SPI register located at address Fh. This register has no other purpose than debugging SPI. The register is read/write accessible, and the register contents has no impact on any other device functionality. So, reading/writing does not change device in any way. To perform the second test, there are multiple read and write conditions that should be performed consecutively. The process is to read the scratch pad register, verify the value is as expected, then write a new value. This process repeats a few times. A suggested flow uses the following steps:

1. Read: Verify address Fh contains 0x00 (default condition)
2. Write: Write byte 0x55 to address Fh
3. Read: Verify address Fh contains 0x55
4. Write: Write byte 0xAA to address Fh
5. Read: Verify address Fh contains 0xAA
6. Write: Write byte 0xFF to address Fh
7. Read: Verify address Fh contains 0xFF
8. Write: Write byte 0x00 to address Fh
9. Read: Verify address Fh contains 0x00

If this test is completed successfully, where success is accurate data reads and writes, then the SPI bus is ready for communication. Further configurations can be written to device if non-default operation is desired. Please refer to specific device data sheet for full register mapping.