There are multiple special use pins on the TCAN284XX/TCAN285XX lines of devices that go beyond communication and power management. The pins are: the WAKEx pins, GFO pin, SW pin, LIMP Pin, nRST pin, and nINT pin.

The WAKEx pins (WAKE1, WAKE2, and WAKE3) are high voltage capable local wake-up pins. The pins can be configured to wake the device up from both rising and falling edge trigger. The pins can also be configured to wake up due to a pulse signal. By default, all the wake signals are active and set to watch for either rising or falling edge triggers. There are four primary registers to alter configurations of the WAKEx pins. These are the WAKE_PIN_CONFIG registers (1-4) - 11h, 12h, 2Ah, and 2Bh. These registers are where wake level, status, wake signal selection, and special features are accessed. The TCAN284XEVM allows for easy testing of Local Wake Ups (LWU) using the WAKEx pins. All three WAKEx signals are routed to J39 for easy access to connect the WAKEx signal to external sensor or other WAKEx signal source. The WAKEx signals can also be pulled up to either HSS4, VSUP, or VCC1 through J36 (WAKE1), J37 (WAKE2), J38 (WAKE3). When the WAKEx pins are pulled up to a supply voltage and S3, S4, or S5 are pushed, a high to low transition takes place on the WAKEx pin associated with the switch pressed. The last example shows static wake, but the WAKEx pins can also be used for cyclic sensing wake which minimizes current in sleep, In this mode, HSS4 periodically turns on, and the WAKEx with cyclic sensing wake selected and compares WAKEx state to previous state. If the states are different the SBC wakes up.

The WAKEx pins can also have some special features that go beyond a LWU, with WAKE1 and WAKE2 aiding battery monitoring applications and WAKE3 acting a direct drive source for controlling any of the HSS blocks available. For using WAKE1 and WAKE2 in aid of battery monitoring applications please see section Potential Modifications for more information as while this board does support Vbat monitoring. A few components must be added. For direct drive the HSSx pin that is to be controlled by WAKE3 needs to be configured for direct drive mode and then WAKE3 acts as an enable switch for the configured HSSx block.

The next special use pin is the GFO. This pin is truly a generic general-purpose output pin. To configure the pin, functionality can be accessed in register 29h. By default, the GFO pin is a simple output pin that can have the state modified through bit 4 in register 29h. The pin can also be used a specific interrupt flag including LDO Error, WD error, LWU, Bus Wakeup Request (WUP), Restart Counter Exceeded, or a CAN bus fault flag. This pin can be accessed on header block J29.

Another special use pin is the SW pin, which has already been touched on in this document. This pin can be thought of as a prototyping/debug pin. During initial development is strongly suggested to hold SW pin in the active state until testing with the Watchdog (WD) begins. In the default state, holding the pin high disables watchdog actions. Meaning that the watchdog timer is still functioning but WD timer events do not cause related WD actions such as putting the device into a different functional mode. The pins active state can be changed to low. Another use of the SW pin is to work as a digital wake-up pin for the SBC while the SBC mode is in sleep mode. This offers a way at a system level to potentially wake the SBC from sleep by using SW as a digital wake up. The SW pin behavior can be modified at register address Eh. The SW pin, if not used for debug/development mode, can be accessed through header block J23.

The next special use pin is LIMP, the LIMP pin is for the limp home function and is an open-drain, active low, output. The pin is used for a limp home mode if the watchdog has timed out causing a reset. The pin is pulled up with an external resistor connected to the battery supply, VSUP. For the LIMP pin to be turned off, the watchdog error counter must reach zero from correct input triggers. If programmed any event that triggers the fail-safe mode also turns on the LIMP pin. The state of this pin can be read back by setting DEVICE_CONFIG register 8'h1A[6] LIMP_RD_EN to 1b. The state of the LIMP pin active (on) or inactive (off) can be read back from LIMP_STATE at 8'h1A[5]. The LIMP pin can be accessed through J15, and J15 can also be used to enable the LIMP indicator LED.

Next, the nRST pin. Which is a bi-directional open drain reset pin for the SBC. The pull-up resistor is integrated and pulled to VCC1. This pin watches for a high to low transition on the input when the device is not in restart mode and VCC1 is present. If a long enough pulse is detected, the device enters restart mode, EEPROM is reloaded, and any default configurations is reimplemented. When the device enters restart mode, the nRST pin pulls low to indicate to downstream devices the SBC is in restart mode. The amount of time the nRST pin is low depends on the method of entry into restart mode and if the LDO (VCC1) is active when device enters restart mode. This pin can be accessed on EVM through J11, and can be configured at register address 29h. S1 can be pressed to initiate a reset on the SBC.

Finally, the nINT pin. The pin flags the controller, or whatever device is connected to nINT pin, if there is an interrupt is generated by device operation. This signal can be accessed through J29 and is an active low flag.