Using the SPI Interface With TRF7960

One of the microcontroller interfacing options available for the TRF7960 is the SPI with SS*. This is also known as 4-wire hardware SPI mode. The TRF7960 device acts as the slave device and the microcontroller or DSP is the master in this configuration.

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1 TRF7960 - SPI With SS* Mode Errata

It is important to note that there are some nonstandard conditions when the TRF7960 is operated in the SPI mode. Table 1 lists these conditions and the software patches to work around them.

Table 1. Nonstandard Conditions

Condition	Software Fix
SCLK clock polarity switch needed when read operation (single or continuous) is executed.	Firmware fix to switch clock polarity between writes and reads (see Section 1.1).
IRQ Status register is not automatically cleared after reading.	Dummy read is needed to clear the contents of IRQ status register and hence drive the IRQ pin low (see Section 1.2).
All stand-alone (single-byte) direct commands need additional clock cycle to work. An example is the slot markers (EOF) for ISO 15693 do not work in SPI mode.	All direct command functions need to have this additional SW fix. Direct commands like “Transmit Next Slot” needs to have additional SCLK cycle before SS* goes high (see Section 1.3).
Some of the registers (RX wait time, RX no response wait time) do not take default values when the appropriate protocol is chosen in the ISO control register.	Manually program these defaults again in the initialization routine (see Section 1.4).
Transmitting one byte through the FIFO.	Split the command (See Section 1.5).

The serial interface is in reset while the SS* signal is high. Serial Data-In (MOSI) changes on the falling edge, and are validated in the reader on the rising edge (see Figure 1). Communication is terminated when SS* signal goes inactive (high). All words must be 8 bits long with the MSB transmitted first.

Figure 1. Serial - SPI Interface Communication (Write Mode)

1.1 SCLK Polarity Switch

The SPI read operation is shown in Figure 2 below.

Figure 2. Serial - SPI Interface Communication (Read Mode)

The read command is sent out on the MOSI pin, MSB first in the first 8 clock cycles. MOSI data changes on the falling edge, and is validated in the reader on the rising edge (see Figure 2). During the write cycle the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the 8th rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO pin at the falling edge of SCLK. It takes 8 clock edges to read out the full byte (MSB first).

NOTE

When using the hardware SPI (for example, a MSP430 hardware SPI) to implement the above feature, care must be taken to switch the SCLK polarity after write phase for proper read operation. The example clock polarity for the MSP430-specific environment is shown in the box above. Refer to the USARTSPI chapter for any specific microcontroller family for further information on the setting the appropriate clock polarity.

This clock polarity switch NEEDS to be done for all read (single, continuous) operations.

The MOSI (serial data out) should not have any transitions (all high or all low) during the read cycle. Also, the SS* should be low during the whole write and read operation.

The clock polarity switch is illustrated by the following pseudo code. This code refers specifically to the MSP430 platform. See the data sheet of the relevant microcontroller for your design.

   *pbuf = (0x40 | *pbuf);        // address, read, single
   *pbuf = (0x5f &*pbuf);         // register address
   while (!(IFG2 & UCB0TXIFG));   // USCI_B0 TX buffer ready?
   UCB0TXBUF = *pbuf;             // Previous data to TX, RX
   //while (!(IFG2 & UCB0RXIFG));
   temp=UCB0RXBUF;
   UCB0CTL1 |= UCSWRST;
   UCB0CTL0 &= ~UCCKPH;	      // switch clock polarity for read
   UCB0CTL1 &= ~UCSWRST;

   SPIStartCondition();           // SCLK High/Low to complete the cycle
   P3SEL |= BIT3;
   while (!(IFG2 & UCB0TXIFG));   // USCI_B0 TX buffer ready?
   UCB0TXBUF = 0x00;              // Receive initiated by a dummy TX write???

   while (!(IFG2 & UCB0RXIFG));
   _NOP();
   _NOP();
   *pbuf = UCB0RXBUF;
   pbuf++;
   lenght--;
   UCB0CTL0 |= UCCKPH;        // revert to original clock polarity

Figure 3 shows the continuous read operation.

Figure 3. SPI Interface Communication (Continuous Read Mode)

1.2 IRQ Status Register Read

NOTE

Special steps are needed when you read the TRF796x IRQ status register (register address 0x0C) in SPI mode. The status of the bits in this register are cleared after a “dummy read”. The following steps need to be followed when reading the IRQ status register.

Write in command 0x6C: read 'IRQ status' register in continuous mode (8 clocks).
Read out the data in register 0x0C (8 clocks).
Generate another 8 clocks (as you were reading the data in register 0x0D) but ignore the MISO data line.

This is shown in Figure 4.

Figure 4. SPI Interface Communication (IRQ Status Register Read)