SLOA140B April   2009  – November 2018 TRF7960 , TRF7960A , TRF7961 , TRF7962A , TRF7963A

 

  1.   Using the SPI Interface With TRF7960
    1.     Trademarks
    2. 1 TRF7960 - SPI With SS* Mode Errata
      1. 1.1 SCLK Polarity Switch
      2. 1.2 IRQ Status Register Read
      3. 1.3 Direct Command Processing
      4. 1.4 Initialization of Derivative Registers
      5. 1.5 Transmitting One Byte Through the FIFO
      6. 1.6 Extra Dummy Bytes on RX
      7. 1.7 Timing Conditions for MOSI With Respect to S_CLK
  2.   Revision History

1.6 Extra Dummy Bytes on RX

A specific condition can cause the TRF7960 to output two additional dummy bytes of data when reading the FIFO after an RX operation. This occurs when the MOSI line is left high after issuing the direct command to continuous read from the TRF7960 FIFO. The MOSI line can left high due to not properly resetting the SPI module while changing the SCLK polarity for the read operation. Figure 5 shows the root cause of this output.

ExtraBytesRxSS1.pngFigure 5. Screenshot With Root Cause

To fix this, ensure the SPI module is properly reset in the MCU when toggling the SCLK polarity between read and write operations. This should force the MOSI line back low and resolve the issue. Figure 6 shows the updated firmware, and Figure 7 shows the signals after correction.

ExtraBytesRxSS2.pngFigure 6. Screenshot of Adjusted Firmware
ExtraBytesRxSS3.pngFigure 7. Screenshot With Issue Fixed