4.1 What are the software differences between TRF7960A and TRF7970A?

As the TRF7960A is an older version of the TRF7970A, there are a number of differences with handling it. When using TI firmware projects for the TRF7970A that do not natively support the TRF79xxA devices covered in this document, the following changes must be applied:

1. FIFO length difference between the TRF7970A and TRF7960A
   • The TRF7970A has a 127-byte FIFO, but the TRF7960A only has a 12-byte FIFO. This means the FIFO buffer needs to be managed when transmitting or receiving more than 12 bytes of data.
   • Monitoring the FIFO watermark through IRQ interrupts lets data be read out before the FIFO overflows during receive operations, or ensures that enough data is loaded into the FIFO during transmit operation.
2. SPI Handling
   • The TRF7960A requires special SPI handling for the following situations:
     • SCLK polarity switch between SPI reads and SPI writes
     • Clearing the IRQ Status register
     • Sending certain direct commands
   • Review Using the SPI Interface With TRF7960 for full details of how to handle the SPI correctly for each of the above items.
3. The TRF7960A does not always take on the correct default register settings when the ISO Control register is written for specific protocols. Specifically, the RX No Response Wait Time register (0x07) and the RX Wait Time register (0x08) are affected by this. Use the following list to properly configure these registers after each write to the ISO Control register:
   • ISO Control is set for ISO/IEC 14443A and ISO/IEC 14443B
     • RX No Response Wait Time register (0x07) = 0x0E
     • RX Wait Time register (0x08) = 0x07
   • ISO Control is set for ISO15693
     • RX No Response Wait Time register (0x07) = 0x15
     • RX Wait Time register (0x08) = 0x1F
   • ISO Control is set for FeliCa
     • RX No Response Wait Time register (0x07) = 0x0E
     • RX Wait Time register (0x08) = 0x01
4. When reading out the FIFO Status register (0x1C), the actual number of bytes within the FIFO is 1 byte larger than the value returned. For example, if reading out the FIFO Status register resulted in a returned value of 0x04, then the actual number of bytes within the FIFO buffer is 0x05.
5. The TRF7960A does not always trigger an IRQ when the RX operation has been completed (IRQ Status = 0x40) when the FIFO watermark IRQ is triggered during RX (IRQ Status = 0x60).
   • To handle this, a 5 millisecond time-out should be used every time an IRQ Status of 0x60 is received to check the IRQ Status register if no IRQ interrupt is received.