SLUAA17A August   2020  – October 2023 BQ79600-Q1

 

  1.   1
  2.   BQ79600-Q1 Software Design Reference
  3.   Trademarks
  4. 1Command Frames
    1. 1.1 Structure
      1. 1.1.1 Initialization Byte
      2. 1.1.2 Device ID Address
      3. 1.1.3 Register Address
      4. 1.1.4 Data
      5. 1.1.5 CRC
    2. 1.2 Command Frame Template Tables
    3. 1.3 Read Register and Write Register Functions
      1. 1.3.1 ReadReg/SpiReadReg
      2. 1.3.2 WriteReg/SPIWriteReg
      3. 1.3.3 Packet Types Available in Sample Code
  5. 2Quick Start Guide
    1. 2.1 Wake Sequence
    2. 2.2 Auto-Addressing
      1. 2.2.1 Steps
      2. 2.2.2 Example Commands for a Stack of 3 Devices
    3. 2.3 Read Cell Voltages
      1. 2.3.1 Steps
      2. 2.3.2 Example Commands for a Stack of 3 Devices
      3. 2.3.3 Convert to Voltages
    4. 2.4 Reverse Addressing
      1. 2.4.1 Steps
      2. 2.4.2 Example Commands for a Stack of Three Devices
  6. 3Revision History

2.2.2 Example Commands for a Stack of 3 Devices

B0 03 43 00 E7 D4       //Step 1 (dummy write OTP_ECC_DATAIN1 to sync DLL) 
B0 03 44 00 E5 E4       //Step 1 (dummy write OTP_ECC_DATAIN2 to sync DLL) 
B0 03 45 00 E4 74       //Step 1 (dummy write OTP_ECC_DATAIN3 to sync DLL) 
B0 03 46 00 E4 84       //Step 1 (dummy write OTP_ECC_DATAIN4 to sync DLL) 
B0 03 47 00 E5 14       //Step 1 (dummy write OTP_ECC_DATAIN5 to sync DLL)
B0 03 48 00 E0 E4       //Step 1 (dummy write OTP_ECC_DATAIN6 to sync DLL)
B0 03 49 00 E1 74       //Step 1 (dummy write OTP_ECC_DATAIN7 to sync DLL)
B0 03 4A 00 E1 84       //Step 1 (dummy write OTP_ECC_DATAIN8 to sync DLL)
D0 03 09 01 0F 74       //Step 2 (enable auto-addressing mode)
D0 03 06 00 CB 44       //Step 3 (set bridge device address DIR0_ADDR = 0)
D0 03 06 01 0A 84       //Step 3 (set stack 1 device address DIR0_ADDR = 1)
D0 03 06 02 4A 85       //Step 3 (set stack 2 device address DIR0_ADDR = 2)
D0 03 06 03 8B 45       //Step 3 (set stack 3 device address DIR0_ADDR = 3)
D0 03 08 02 4E E5       //Step 4 (set all stacked devices as stack)
90 03 03 08 03 53 98    //Step 5 (set stack 3 as both stack and top of stack)
A0 03 43 00 E3 14       //Step 6 (dummy read OTP_ECC_DATAIN1 to sync DLL)
A0 03 44 00 E1 24       //Step 6 (dummy read OTP_ECC_DATAIN2 to sync DLL)
A0 03 45 00 E0 B4       //Step 6 (dummy read OTP_ECC_DATAIN3 to sync DLL)
A0 03 46 00 E0 44       //Step 6 (dummy read OTP_ECC_DATAIN4 to sync DLL)
A0 03 47 00 E1 D4       //Step 6 (dummy read OTP_ECC_DATAIN5 to sync DLL)
A0 03 48 00 E4 24       //Step 6 (dummy read OTP_ECC_DATAIN6 to sync DLL)
A0 03 49 00 E5 B4       //Step 6 (dummy read OTP_ECC_DATAIN7 to sync DLL)
A0 03 4A 00 E5 44       //Step 6 (dummy read OTP_ECC_DATAIN8 to sync DLL)

Explanation of the first stack write command frame (B0 03 43 00 E7 D4):

  • B0 = stack write of one byte
  • 0343 = register address
  • 00 = write value 0x00
  • E7D4 = CRC

Explanation of the first broadcast write command frame (D0 03 09 01 0F 74):

  • D0 = broadcast write of one byte
  • 0309 = register address
  • 01 = write value 0x01
  • 0F74 = CRC

Explanation of first single device write command frame (90 03 03 08 03 53 98):

  • 90 = single device write of one byte
  • 03 = device address
  • 0308 = register address
  • 03 = write value 0x03
  • 5398 = CRC
Explanation of first stack read command frame (A0 03 43 00 E3 14):

  • A0 = stack read
  • 0343 = register address
  • 00 = read one byte of data
  • E314 = CRC