3 Output Capacitance Upper Limit for Internally-Compensated PCM Buck Converter

For system loop stability, a –20 dB/dec slope near crossover frequency is ideal for loop gain, since that can normally bring sufficient phase margin⁽³⁾.

Figure 2-2 shows the loop gain slope of the PCM converter changes from 0 to –20 dB/dec at the initial pole frequency, f_{P1_EA}. At pole f_{P_OUT}, the loop gain slope changes to –40 dB/dec. With the compensation of zero f_{Z_EA}, the gain slope becomes –20 dB/dec and the gain curve crosses 0 dB with this slope. That could bring sufficient phase margin for the converter.

Figure 3-1(a) illustrates that the converter crossover frequency f_c becomes lower with reduced pole frequency f_{P_OUT}. If f_c < f_{Z_EA}, the zero f_{Z_EA} is out of crossover frequency and loop gain crosses 0 dB with a –40 dB/dec slope. If these conditions occur, they may cause insufficient phase margin.

Equation 4 shows that pole f_{P_OUT} is inversely related with output capacitance C_O. Reducing C_O can make both f_{P_OUT} and f_c increase. As shown in Figure 3-1(b), after increasing the pole frequency f_{P_OUT}, f_{Z_EA} could be smaller than the crossover frequency f_c and the loop gain crosses 0 dB with a –20 dB/dec slope. These conditions could normally ensure converter phase margin.

Based on the previous analysis, use Equation 6 to calculate the limitation for –20 dB/dec slope at gain crossover frequency:

As Equation 2 shows, f_{Z_EA} is fixed at 10.6 kHz for TPS62933. To get the relation between output capacitance C_o and f_c, first calculate the relation between gain and frequency using Equation 7 and Equation 8.

where

• A_{P_OUT} is the loop gain at frequency f_{P_OUT}

Equation 7 and Equation 8 can be simplified as:

With Equation 4, Equation 6, and Equation 10, the upper limit for output capacitance is calculated using Equation 11.

Substituting parameters in Equation 1 and Equation 2, the upper limit for TPS62933 is:

Normally for a buck converter, a 45 degree phase margin can be achieved with –20 dB/dec slope at gain crossover frequency. But for a buck regulator with peak current-mode control, when a larger inductance is used, the frequency of the inner current loop pole f_{P_ci} will be lower and bring more phase drop at the gain crossover frequency. These conditions may cause a phase margin lower than 45 degrees, even with –20 dB/dec crossing. Therefore, the capacitance upper limit for a 45 degree phase margin is also deducted in this section.

Figure 3-2 is a bode plot of a PCM buck converter with –20 dB/dec crossing. f_{Z_OUT} and f_{P2_EA} are normally at very high frequency so their effects on phase margin at gain crossover frequency can be ignored at first. Pole f_{P1_EA} is at a very low frequency and brings about –90° phase drop at gain crossover frequency.

Next, calculate the phase margin using Equation 13. Equation 14 constitutes the limitation to make the phase margin larger than 45 degrees.

Calculate gain crossover frequency f_cross using Equation 15, Equation 16 and Equation 17, based on Figure 3-2.

Derive f_cross using equation Equation 18:

Substituting Equation 1, Equation 2, and Equation 4 into Equation 18, f_cross is expressed with:

Substituting Equation 2, Equation 4, Equation 5, and Equation 19 into Equation 14 and ignoring ESR impacts, the upper limit for output capacitance for phase margin restriction is calculated using the following example equation:

(50*(111936*IOUT - 4460544))/(441013* IOUT *VOUT*(422400/ IOUT + (8954880000/ IOUT + 178421760000/ IOUT ^2 + (2500* VIN ^2* fsw ^2)/(24649*(4356000*L + VIN - 2* VOUT)^2) - (3180000* VIN *fsw)/(157*(4356000*L + VIN - 2* VOUT)) + (84480000* VIN * fsw)/(157* IOUT *(4356000*L + VIN - 2* VOUT)) - (267632640000* VIN * fsw)/(8321* IOUT ^2*(4356000*L + VIN - 2* VOUT)) + (10560000* VIN ^2* fsw ^2)/(1306397* IOUT *(4356000*L + VIN - 2* VOUT)^2) + (11151360000* VIN ^2* fsw ^2)/(69239041* IOUT ^2*(4356000*L + VIN - 2* VOUT)^2) + 112360000)^(1/2) - (50* VIN * fsw)/(157*(4356000*L + VIN - 2* VOUT)) - (105600* VIN * fsw)/(8321* IOUT *(4356000*L + VIN - 2* VOUT)) + 10600))

Since the expression for output capacitance upper limit with phase margin restriction is very complicated, an example of how to use Microsoft® Excel® or MATLAB® for the calculation is introduced in Section A.