SLUAAP7 January   2024 BQ76905 , BQ76907

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Cell Balancing Circuit Considerations
    1. 2.1 Internal Cell-Balancing Circuit Design
    2. 2.2 External Cell-Balancing Circuit Design Using N-Channel FETs
    3. 2.3 External Cell-Balancing Circuit Design Using BJTs
  6. 3Considerations for a Host-Balancing Algorithm
  7. 4Timing Information
  8. 5Debugging Common Issues With Cell Balancing
    1. 5.1 Using a Resistor Divider as a Cell Simulator
    2. 5.2 Cell Balancing Troubleshooting
  9. 6Summary
  10. 7References

5.2 Cell Balancing Troubleshooting

  1. Why does cell balancing stop after a few seconds?
    The balancing automatically stops after 20 seconds. It is the user responsibility to resend the 0x0083 command.
  2. Why do I need to send the Cell Balancing command multiple times when using the Commdand Sequence tab in BQStudio?
    Make sure the Auto Refresh and the Scan icons are OFF so that the EV2400 does not keep talking to the device while balancing.
  3. Why my multimeter reports a lower balancing current and lower voltage when balancing?
    The multimeter reports an average value because it cannot keep up with the measurement frequency. A scope must be used to be able to capture these measurements.
  4. Why is the cell balancing not working after sending 0x0083 subcommand?
    A checksum and length must be sent. Please see the following example.
    Cell 1 (VC1) Cell Balancing command
    • W: 10 3E 83 00 02 (writes to cell 1)
    • W: 10 60 7A 05 (checksum and length)
    • R: 10 40 2 (reads active balancing cells)
  5. Where can I probe to see cell balancing happening at a particular cell?
    You can be probing at the VCx pins if using internal balancing. If using external balancing circuitry, it is recommended to probe at the external balancing resistor to see if the FET or BJT is ON.
  6. How can I calculate the maximum allowed dissipated power through the internal balancing FETs?
    P = (Imax)2 × RDS(ON)

    Where Imax is the maximum cell balancing current at each cell (50 mA)

    Where the typical internal cell balancing resistance (RDS(ON) for the internal FET) is 80Ω