SLUAAY1 October   2024 UCC28064A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Interleaving PFC Principle of Operation
  6. 3Original PFC Design with Internal Line Feed-Forward block
  7. 4Current Phenomenon of Operating With UCC28064A Internal Line Feed Forward Function
  8. 5Achieving Adaptive Current Control PFC With UCC28064A
  9. 6Test Results Comparing Original PFC Design to Adaptive PFC Design
  10. 7Summary
  11. 8References

2 Interleaving PFC Principle of Operation

The UCC28064A device contains the control circuits for two parallel-connected boost pulse-width modulated (PWM) power converters. The boost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage on the error amplifier output (COMP pin). Each power converter then turns off the power MOSFET until current in the boost inductor decays to zero (as sensed on the zero current detection inputs, ZCDA and ZCDB). After the inductor demagnetizes, the power converter starts another cycle. This cycle process produces a triangular waveform of current, with peak current set by the on-time and the instantaneous power mains input voltage, VIN(t) value, as shown in Equation 1.

Equation 1. I peak = VIN × Ton / L

The average line current is exactly equal to half of the peak line current, as shown in Equation 2.

Equation 2. I avg = 1/2 × (VIN × Ton / L)

When the Ton and L values are essentially constant during an AC-line period, the resulting triangular current waveform during each switching cycle has an average value proportional to the instantaneous value of the rectified AC-line voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a near-unity power factor

Interleaving PFC Block Introduction Figure 2-1 Interleaving PFC Block Introduction