SLUS670C JULY   2005  – January 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation
      2. 7.3.2  Adaptive On-Time Control
      3. 7.3.3  Light Load Operation
      4. 7.3.4  Forced PWM Operation
      5. 7.3.5  5-V, 100-mA, LDO and Switchover (VREG5)
      6. 7.3.6  3.3-V, 100-mA, LDO and Switchover (VREG3)
      7. 7.3.7  2-V, 50-uA Sink - Source Reference (VREF2)
      8. 7.3.8  Low-Side Driver
      9. 7.3.9  High-Side Driver
      10. 7.3.10 Soft-Start
      11. 7.3.11 Soft-Stop
      12. 7.3.12 Powergood
      13. 7.3.13 Current Sensing and Overcurrent Protection
      14. 7.3.14 Overvoltage Protection
      15. 7.3.15 Undervoltage Protection
      16. 7.3.16 5-V Supply and UVLO Protection
      17. 7.3.17 VIN Line Sag Protection (Dynamic UVP)
      18. 7.3.18 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Current Mode
        1. 7.4.1.1 Current Mode Operation
      2. 7.4.2 D-Cap Mode
        1. 7.4.2.1 D-Cap Mode Operation
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS51120 is typically used as a dual-synchronous buck controller, which convert an input voltage ranging from 4.5V to 28 V, to output voltage ranging 1V to 5.5 V, targeted for notebook I/O and low voltage system bus supply solutions.

8.2 Typical Application

v05074_lus670.gifFigure 32. D-Cap Mode, Fixed 5-V / 6-A, 3.3-V/6-A, RDS(on) Sensing

8.2.1 Design Requirements

Table 6. Design Parameters

DESIGN PARAMETER VALUE
Input Voltage Range 4.5 V to 28 V
Channel 1 Output Voltage 5 V
Channel 1 Output Current 6 A
Channel 2 Output Voltage 3.3 V
Channel 2 Output Current 6 A

8.2.2 Detailed Design Procedure

  1. Determine output voltage. Since 5 V and 3.3 V is the default fixed output voltage, tie VFB1 and VFB2 to V5FILT to choose the internal feedback resistor divider.
  2. Choose control mode. Tie COMP1 and COMP2 to V5FILT to choose D-CAP control mode.
  3. Choose switching frequency. Tie TONSEL to VREF2, choose 280kHz/430kHz for channel1 and channel2 respectively.
  4. Choose the inductor. To make the inductor ripple current at ½ of maximum output current, calculate inductance according to Equation 12 as below:
    5. Equation 21. equation1_slus670.gif
    Equation 22. equation2_slus670.gif

    4.7-uH and 2.2-uH inductor is chosen for channel1 and channel2 respectively. Check inductor specification, make sure the saturation current is higher than peak inductor current in this application with enough room.

  5. Choose the output capacitor. To get an acceptable jitter level, approximately 15mV ripple at comparing point is needed. Refer to Equation 20. This require the minimum ESR of output capacitors for channel1 and channel2 is:
    6. Equation 23. ESR1 = (Vout1 × 0.015) ÷ Iripple1 = (5 V × 0.015) ÷ 3 A = 25 mΩ
    Equation 24. ESR2 = (Vout2 × 0.015) ÷ Iripple2 = (3.3 V × 0.015) ÷ 3 A = 16.5 mΩ

Choose 2pcs 150-uF/50-mΩ SP-CAP in parallel, the equivalent capacitance and ESR is 300 uF and 25 mΩ, meet above requirement.

0dB frequency f0 calculated as below:

Equation 25. equation3_slus670.gif

F0 is much less than 1/3 of the switching frequency, loop should be stable.

8.2.3 Application Curves

ch1_5a_lus670.gifFigure 33. 5-V Load Transient Response
five_start_lus670.gifFigure 35. 5-V Startup Waveforms
five_sw_lus670.gifFigure 37. 5-V Switchover Waveforms
five_sstop_lus670.gifFigure 39. 5-V Soft-Stop Waveforms
ch2_5a_lus670.gifFigure 34. 3.3-V Load Transient Response
three_start_lus670.gifFigure 36. 3.3-V Startup Waveforms
three_sw_lus670.gifFigure 38. 3.3-V Switchover Waveforms
three_sstop_lus670.gifFigure 40. 3.3-V Soft-Stop Waveforms