SLUS774C AUGUST   2007  – December 2014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3  Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Voltage Reference
      2. 7.3.2  Oscillator
      3. 7.3.3  Input Undervoltage Lockout (UVLO) and Startup
      4. 7.3.4  Enable and Timed Turn On of the Outputs
      5. 7.3.5  Output Voltage Sequencing
      6. 7.3.6  Soft-Start
      7. 7.3.7  Output Voltage Regulation
      8. 7.3.8  Feedback Loop and Inductor-Capacitor (L-C) Filter Selection
      9. 7.3.9  Inductor-Capacitor (L-C) Selection
      10. 7.3.10 Maximum Output Capacitance
      11. 7.3.11 Minimum Output Capacitance
      12. 7.3.12 Modifying The Feedback Loop
        1. 7.3.12.1 Using High-ESR Output Capacitors
        2. 7.3.12.2 Using All Ceramic Output Capacitors
      13. 7.3.13 Example: TPS54386 Buck Converter Operating at 12-V Input, 3.3-V Output and 400-mA(P-P) Ripple Current
      14. 7.3.14 Bootstrap for the N-Channel MOSFET
      15. 7.3.15 Light Load Operation
      16. 7.3.16 SW Node Ringing
        1. 7.3.16.1 SW Node Snubber
        2. 7.3.16.2 Bootstrap Resistor
      17. 7.3.17 Output Overload Protection
      18. 7.3.18 Operating Near Maximum Duty Cycle
      19. 7.3.19 Dual Supply Operation
      20. 7.3.20 Cascading Supply Operation
      21. 7.3.21 Multiphase Operation
      22. 7.3.22 Bypass and FIltering
      23. 7.3.23 Overtemperature Protection and Junction Temperature Rise
      24. 7.3.24 Power Derating
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum Input Voltage
      2. 7.4.2 ENx Control
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 12-V to 5-V and 3.3-V Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Duty Cycle Estimation
          2. 8.2.1.2.2  Inductor Selection
          3. 8.2.1.2.3  Rectifier Diode Selection
          4. 8.2.1.2.4  Output Capacitor Selection
          5. 8.2.1.2.5  Voltage Setting
          6. 8.2.1.2.6  Compensation Capacitors
          7. 8.2.1.2.7  Input Capacitor Selection
          8. 8.2.1.2.8  Boot Strap Capacitor
          9. 8.2.1.2.9  ILIM
          10. 8.2.1.2.10 SEQ
          11. 8.2.1.2.11 Power Dissipation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 24-V to 12-V and 24-V to 5-V
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 5-V to 3.3V and 5-V to 1.2 V
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PowerPAD Package
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Definition of Symbols
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

10 Layout

10.1 Layout Guidelines

The layout guidelines presented here are illustrated in the PCB layout examples given in Figure 51 and Figure 52.

  • The PowerPAD must be connected to a low current (signal) ground plane having a large copper surface area to dissipate heat. Extend the copper surface well beyond the IC package area to maximize thermal transfer of heat away from the IC.
  • Connect the GND pin to the PowerPAD through a 10-mil (.010 in, or 0.0254 mm) wide trace.
  • Place the ceramic input capacitors close to PVDD1 and PVDD2; connect using short, wide traces.
  • Maintain a tight loop of wide traces from SW1 or SW2 through the switch node, inductor, output capacitor and rectifier diode. Avoid using vias in this loop.
  • Use a wide ground connection from the input capacitor to the rectifier diode, placed as close to the power path as possible. Placement directly under the diode and the switch node is recommended.
  • Locate the bootstrap capacitor close to the BOOT pin to minimize the gate drive loop.
  • Locate voltage setting resistors and any feedback components over the ground plane and away from the switch node and the rectifier diode to input capacitor ground connection.
  • Locate snubber components (if used) close to the rectifier diode with minimal loop area.
  • Locate the BP bypass capacitor very close to the IC; a minimal loop area is recommended.
  • Locate the output ceramic capacitor close to the inductor output terminal between the inductor and any electrolytic capacitors, if used.

10.2 Layout Example

pcb_top_lus774.gifFigure 51. Top Layer Copper Layout and Component Placement
pcb_bottom_lus774.gifFigure 52. Bottom Layer Copper Layout

10.3 PowerPAD Package

The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) work well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. (See the Related Documentation section.)