SLUS794F November   2007  – April 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Interleaving
      2. 7.3.2  Programming the PWM Frequency and Maximum Duty-Cycle Clamp
      3. 7.3.3  Frequency Dithering (Magnitude and Rate)
      4. 7.3.4  External Clock Synchronization
      5. 7.3.5  Multi-phase Operation
      6. 7.3.6  VSENSE and VINAC Resistor Configuration
      7. 7.3.7  VSENSE and VINAC Open-Circuit Protection
      8. 7.3.8  Current Synthesizer
      9. 7.3.9  Programmable Peak Current Limit
      10. 7.3.10 Linear Multiplier and Quantized Voltage Feed Forward
      11. 7.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
      12. 7.3.12 Voltage Biasing (VCC and VVREF)
      13. 7.3.13 PFC Enable and Disable
      14. 7.3.14 Adaptive Soft Start
      15. 7.3.15 PFC Start-Up Hold Off
      16. 7.3.16 Output Overvoltage Protection (OVP)
      17. 7.3.17 Zero-Power Detection
      18. 7.3.18 Thermal Shutdown
      19. 7.3.19 Current Loop Compensation
      20. 7.3.20 Voltage Loop Compensation
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Current Calculation
        2. 8.2.2.2 Bridge Rectifier
        3. 8.2.2.3 PFC Inductor (L1 and L2)
        4. 8.2.2.4 PFC MOSFETs (M1 and M2)
        5. 8.2.2.5 PFC Diode
        6. 8.2.2.6 PFC Output Capacitor
        7. 8.2.2.7 Current Loop Feedback Configuration (Sizing of the Current Transformer Turns Ratio and Sense Resistor (RS)
        8. 8.2.2.8 Current Sense Offset and PWM Ramp for Improved Noise Immunity
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

DW and PW Packages
20-Pin SOIC and TSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CAOA 12 O Phase A Current Amplifier Output. Output of phase A transconductance current amplifier. Internally connected to the inverting input of phase A PWM comparator for trailing-edge modulation. Connect the current regulation loop compensation components between this pin and GND.
CAOB 11 O Phase B Current Amplifier Output. Output of phase B transconductance current amplifier. Internally connected to the inverting input of phase B PWM comparator for trailing-edge modulation. Connect the current regulation loop compensation components between this pin and GND.
CDR 1 I Dither Rate Capacitor. Frequency-dithering timing pin. An external capacitor to GND programs the rate of oscillator dither. Connect the CDR pin to the VREF pin to disable dithering.
CSA 9 I Phase A Current Sense Input. During the ON-time of GDA, CSA is internally connected to the inverting input of phase A current amplifier through the current synthesis stage.
CSB 8 I Phase B Current Sense Input. During the ON-time of GDB, CSB is internally connected to the inverting input of phase B current amplifier through the current synthesis stage.
DMAX 20 I Maximum Duty-Cycle Resistor. Maximum PWM duty-cycle programming pin. A resistor to GND sets the PWM maximum duty-cycle based on the ratio of RDMX / RRT.
GDA 14 O Phase A Gate Drive. This limited-current output is intended to connect to a separate gate-drive device suitable for driving the phase A switching component(s). The output voltage is typically clamped to 13.5 V.
GDB 17 O Phase B Gate Drive. This limited-current output is intended to connect to a separate gate-drive device suitable for driving the phase B switching component(s). The output voltage is typically clamped to 13.5 V.
GND 16 I/O Device Ground Reference. Connect all compensation and programming resistor and capacitor networks to this pin. Connect this pin to the system through a separate trace for high-current noise isolation.
IMO 6 O Multiplier Current Output. Connect a resistor between this pin and GND to set the multiplier gain.
PKLMT 10 I Peak Current Limit Programming. Connect a resistor-divider network between VREF and this pin to set the voltage threshold of the cycle-by-cycle peak current limiting comparators. Allows adjustment for desired ΔILB.
RDM
(SYNC)		 2 I Dither Magnitude Resistor. Frequency-dithering magnitude and external synchronization pin. An external resistor to GND programs the magnitude of oscillator frequency dither. When frequency dithering is disabled (CDR > 5 V), the internal master clock synchronizes to positive edges presented on the RDM pin. Connect RDM to GND when dithering is disabled and synchronization is not desired.
RSYNTH 7 I Current Synthesis Down-Slope Programming. Connect a resistor between this pin and GND to set the magnitude of the current synthesizer down-slope. Connecting RSYNTH to VREF disables current synthesis and connect CSA and CSB directly to their respective current amplifiers.
RT 19 I Timing Resistor. Oscillator frequency programming pin. A resistor to GND sets the running frequency of the internal oscillator.
SS 18 I Soft-Start and External Fault Interface. Connect a capacitor to GND on this pin to set the soft-start slew rate based on an internally-fixed, 10-μA current source. The regulation reference voltage for VSENSE is clamped to VSS until VSS exceeds 3 V. Upon recovery from certain fault conditions, a 1-mA current source is present at the SS pin until the SS voltage equals the VSENSE voltage. Pulling the SS pin below 0.6 V immediately disables both GDA and GDB outputs.
VAO 3 O Voltage Amplifier Output. Output of transconductance voltage error amplifier. Internally connected to the multiplier input and the zero-power comparator. Connect the voltage regulation loop compensation components between this pin and GND.
VCC 15 I Bias Voltage Input. Connect a 0.1-μF ceramic bypass capacitor as close as possible to this pin and GND.
VINAC 5 I Scaled AC Line Input Voltage. Internally connected to the multiplier and negative terminal of the current synthesis difference amplifier. Connect a resistor-divider network between VIN, VINAC, and GND identical to the PFC output divider network connected at VSENSE.
VREF 13 O 6-V Reference Voltage and Internal Bias Voltage. Connect a 0.1-μF ceramic bypass capacitor as close as possible to this pin and GND.
VSENSE 4 I Output Voltage Sense. Internally connected to the inverting input of the transconductance voltage error amplifier in addition to the positive terminal of the current synthesis difference amplifier. Also connected to the OVP, PFC enable, and slew-rate comparators. Connect to PFC output with a resistor-divider network.