The UCC28610 brings a new level of performance and reliability to the AC and DC consumer power supply solution.
A PWM modulation algorithm varies both the switching frequency and primary current while maintaining discontinuous or transition mode operation over the entire operating range. Combined with a cascoded architecture, these innovations result in efficiency, reliability, and system cost improvements over a conventional flyback architecture.
The UCC28610 offers a predictable maximum power threshold and a timed response to an overload, allowing safe handling of surge power requirements. Overload fault response is user-programmed for retry or latch-off mode. Additional protection features include output overvoltage detection, programmable maximum on-time, and thermal shutdown.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCC28610 | SOIC (8) | 4.90 mm x 3.91 mm |
PDIP (8) | 9.81 mm x 6.35 mm |
Changes from F Revision (November 2014) to G Revision
Changes from E Revision (September 2012) to F Revision
Changes from D Revision (January 2011) to E Revision
Changes from C Revision (January 2009) to D Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO. | |||
CL | 3 | I | (Current Limit) This pin programs the peak primary inductor current that is reached each switching cycle. Program with a resistor between CL and GND. | |
DRV | 6 | O | (DRiVe) This pin drives the source of an external high voltage power MOSFET. The DRV pin carries the full primary current of the converter. Connect a Schottky diode between DRV and VDD to provide initial bias at start up. | |
FB | 1 | I | (FeedBack) The FB current, IFB, commands the operating mode of the UCC28610. The FB voltage is always 0.7 V. This pin only detects current. | |
GND | 7 | — | (GrouND) This pin is the current return terminal for both the analog and power signals in the UCC28610. This terminal carries the full primary current of the converter. Separate the return path of the bulk capacitor from the return path of FB, ZCD, MOT, and CL. | |
MOT | 4 | I | (Maximum On Time) This pin has three functions:
Functions 1 and 2 are programmed with a resistor between MOT and GND. |
|
VDD | 8 | — | This is the bias supply pin for the UCC28610. It can be derived from an external source or an auxiliary winding. This pin must be decoupled with a 0.1-μF ceramic capacitor placed between VDD and GND, as close to the device as possible. | |
VGG | 5 | — | This pin provides a DC voltage for the gate of the external high voltage MOSFET. This pin must be decoupled with a 0.1-μF ceramic capacitor placed between VGG and GND, as close to the device as possible. This pin also initiates start-up bias through a large value resistor that is connected to the input bulk voltage. | |
ZCD | 2 | I | (Zero Current Detection) This pin has two functions:
|
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Input voltage range | VDD | –0.5 | 25 | V | |
DRV, during conduction | –0.5 | 2.0 | |||
DRV, during non-conduction | 20 | ||||
VGG (2) | –0.5 | 16 | |||
ZCD, MOT, CL (3) | –0.5 | 7 | |||
FB (3) | –0.5 | 1.0 | |||
VDD – VGG | –7 | 10 | |||
Continuous input current | IVGG (2) | 10 | mA | ||
Input current range | IZCD, IMOT, ICL, IFB (3) | –3 | 1 | ||
Peak output current | DRV | -5 | A | ||
DRV, pulsed 200ns, 2% duty cycle | –5 | 1.5 | |||
TJ | Operating junction temperature, | –40 | 150 | °C | |
Lead Temperature (soldering, 10 sec.) | 260 | °C | |||
Tstg | Storage temperature range | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) | 1500 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) | 500 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VDD | Input voltage | 9 | 20 | V | |
VGG | Input voltage from low-impedance source | 9 | 13 | V | |
IVGG | Input current from a high-impedance source | 10 | 2000 | μA | |
RMOT | Resistor to GND | Shutdown/Retry mode | 25 | 100 | kΩ |
Latch-off mode | 150 | 750 | kΩ | ||
RCL | Resistor to GND | 24.3 | 100 | kΩ | |
RZCD1 | Resistor to auxiliary winding | 50 | 200 | kΩ | |
CVGG | VGG capacitor | 33 | 200 | nF | |
CBP | VDD bypass capacitor, ceramic | 0.1 | 1 | μF |
THERMAL METRIC (1) | UCC28610 | UNIT | ||
---|---|---|---|---|
D (SOIC) | P (PDIP) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 117.5 | 56.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 63.7 | 45.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 57.8 | 33.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 15.3 | 22.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 57.3 | 33.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VDD and VGG SUPPLY | ||||||
VGG(OPERATING) | VGG voltage, operating | VDD = 14 V, IVGG = 2.0 mA | 13 | 14 | 15 | V |
VGG(DISABLED) | VGG voltage, PWM disabled | VDD = 12 V, IVGG = 15 μA, IFB = 350 μA | 15 | 16 | 17 | V |
ΔVGG | Rise in VGG clamping voltage during UVLO, GM, or Fault | VGG(DISABLED) – VGG(OPERATING) | 1.75 | 2.00 | 2.15 | V |
IVGG(SREG) | VGG shunt regulator current | VGG = VGG(DISABLED) -100 mV, VDD = 12 V | 6 | 10 | μA | |
ΔVGG(SREG) | VGG shunt load regulation | 10 μA ≤ IVGG ≤ 5 mA, IFB = 350 μA | 125 | 200 | mV | |
VGG(LREG) | VGG LDO regulation voltage | VDD = 20 V, IVGG = – 2 mA | 13 | V | ||
VGG(LREG, DO) | VGG LDO Dropout Voltage | VDD – VGG, VDD = 11 V, IVGG = – 2 mA | 1.5 | 2 | 2.5 | V |
VDD(ON) | UVLO turn-on threshold | 9.7 | 10.2 | 10.7 | V | |
VDD(OFF) | UVLO turn-off threshold | 7.55 | 8 | 8.5 | V | |
ΔVDD(UVLO) | UVLO hysteresis | 1.9 | 2.2 | 2.5 | V | |
IVDD(OPERATING) | Operating current | VDD = 20 V | 2.5 | 3 | 3.7 | mA |
IVDD(GM) | Idle current between bursts | IFB = 350 μA | 550 | 900 | μA | |
IVDD(UVLO) | Current for VDD < UVLO | VDD = VDD(ON) – 100 mV, increasing | 225 | 310 | μA | |
RDS,ON(VDD) | VDD Switch on resistance, DRV to VDD | VGG = 12 V, VDD = 7V, IDRV = 50 mA | 4 | 10 | Ω | |
VDD(FAULT RESET) | VDD for fault latch reset | 5.6 | 6 | 6.4 | V | |
MODULATION | ||||||
tS(HF) (1) | Minimum switching period, frequency modulation (FM) mode | IFB = 0 μA, (1) | 7.125 | 7.5 | 7.875 | μs |
tS(LF) (1) | Maximum switching period, reached at end of FM modulation range | IFB = IFB, CNR3 – 20 μA, (1) | 31 | 34 | 38 | μs |
IDRVpk(max) | Maximum peak driver current over amplitude modulation(AM) range | IFB = 0 μA, RCL = 33. 2 kΩ | 2.85 | 3 | 3.15 | A |
IFB = 0 μA, RCL = 100 kΩ | 0.80 | 0.90 | 1.0 | |||
IDRVpk(min) | Minimum peak driver current reached at end of AM modulation range | IFB, CNR2 + 10 μA, RCL = 33.2 kΩ | 0.7 | 0.85 | 1.1 | A |
IFB, CNR2 + 10 μA, RCL = 100 kΩ | 0.2 | 0.33 | 0.5 | |||
KP | Maximum power constant | IDRVpk(max) = 3 A | 0.54 | 0.60 | 0.66 | W/μH |
IDRVpk(absmin) | Minimum peak driver independent of RCL or AM control | RCL = OPEN | 0.3 | 0.45 | 0.6 | A |
tBLANK(Ilim) | Leading edge current limit blanking time | IFB = 0 μA, RCL = 100 kΩ, 1.2-A pull-up on DRV | 120 | 220 | 450 | ns |
VCL | Voltage of CL pin | IFB = 0 μA | 2.94 | 3 | 3.06 | V |
IFB = (IFB,CNR3 – 20 μA) (1) | 0.95 | 1.00 | 1.10 | |||
IFB,CNR1 (4) | IFB range for FM modulation | IFB increasing, tS = tS(LF), IDRVpk = IDRVpk(max) |
145 | 165 | 195 | μA |
IFB,CNR2 – IFB,CNR1 (4) | IFB range for AM modulation | tS = tS(LF), IDRVpk ranges from IDRVpk(max) to IDRVpk(min) |
35 | 45 | 65 | μA |
IFB,CNR3 – IFB,CNR2 (4) | IFB range for Green Mode (GM) modulation | IFB increasing until PWM action is disabled entering a burst-off state | 45 | 70 | 90 | μA |
IFB, GM-HYST (4) | IFB hysteresis during GM modulation to enter burst on and off states | IFB decreasing from above IFB,CNR3 | 10 | 25 | 40 | μA |
VFB | Voltage of FB pin | IFB = 10 μA | 0.34 | 0.7 | 0.84 | V |
ZERO CROSSING DETECTION | ||||||
ZCD(TH) | ZCD zero crossing threshold | ZCD high to low generates switching period (tS has expired) | 5 | 20 | 50 | mV |
ZCD(CLAMP) | ZCD low clamp voltage | IZCD = –10 μA | -220 | -160 | -100 | mV |
ZCD(START) | ZCD voltage threshold to enable the internal start timer | Driver switching periods generated at start timer rate | 0.1 | 0.15 | 0.2 | V |
tDLY(ZCD) | Delay from zero crossing to Driver turn-on | 150-Ω pull-up to 12-V on DRV | 150 | ns | ||
tWAIT(ZCD) | Wait time for zero crossing detection | Driver turn-on edge generated following tS with previous zero crossing detected | 2 | 2.4 | 2.8 | μs |
tST | Starter time-out period | ZCD = 0 V | 150 | 240 | 300 | |
DRIVER | ||||||
RDS(on)(DRV) | Driver on-resistance | IDRV = 4.0 A | 90 | 190 | mΩ | |
IDRV(OFF) | Driver off-leakage current | DRV = 12 V | 1.5 | 20 | μA | |
RDS(on)(HSDRV) | High-side driver on-resistance | IDRV = –50 mA | 6 | 11 | Ω | |
IDRV(DSCH) | DRV bulk discharge current | VDD open, DRV= 12 V, Fault latch set | 2 | 2.8 | 3.6 | mA |
OVERVOLTAGE FAULT | ||||||
ZCD(OVP) | Overvoltage fault threshold at ZCD | Fault latch set | 4.85 | 5 | 5.15 | V |
tBLANK(OVP) | ZCD blanking and OVP sample time from the turn-off edge of DRV | 0.6 | 1 | 1.7 | μs | |
IZCD(bias) | ZCD Input bias current | ZCD = 5 V | -0.1 | -0.05 | 0.1 | μA |
OVERLOAD FAULT | ||||||
IFB(OL) | Current to trigger overload delay timer | 0 | 1.5 | 3 | μA | |
tOL | Delay to overload fault | IFB = 0 A continuously | 200 | 250 | 325 | ms |
tRETRY | Retry delay in retry mode or after shutdown command | RMOT = 76 kΩ | 750 | ms | ||
RMOT(TH) | Boundary RMOT between latch-off and retry modes | See (2) | 100 | 120 | 150 | kΩ |
SHUTDOWN THRESHOLD | ||||||
MOT(SR) | Shutdown-Retry threshold | MOT high to low | 0.7 | 1 | 1.3 | V |
IMOT | MOT current when MOT is pulled low | MOT = 1 V | –600 | –450 | –300 | μA |
MAXIMUM ON TIME | ||||||
tMOT | Latch-OFF | RMOT = 383 kΩ | 3.43 | 3.83 | 4.23 | μs |
Shutdown-retry | RMOT = 76 kΩ | 3.4 | 3.8 | 4.2 | ||
MOT | MOT voltage | 2.7 | 3 | 3.3 | V | |
THERMAL SHUTDOWN | ||||||
TSD (3) | Shutdown temperature | TJ, temperature rising (3) | 165 | °C | ||
TSD_HYS (3) | Hysteresis | TJ, temperature falling, degrees below TSD (3) | 15 | °C |
The flyback converter is attractive for low power AC/DC applications because it provides output isolation and wide input operating abilities using a minimum number of components. Operation of the flyback converter in Discontinuous Conduction Mode (DCM) is especially attractive because it eliminates reverse recovery losses in the output rectifier and it simplifies control.
The UCC28610 is a flyback controller for 12-W to 65-W, peak AC/DC power supply applications that require both low AC line power during no-load operation and high average efficiency. This controller limits the converter to DCM operation. It does not allow Continuous Conduction Mode (CCM) operation. Forced DCM operation results in a uniquely safe current limit characteristic that is insensitive to AC line variations. The peak current mode modulator does not need slope compensation because the converter operates in DCM.
The operation of the UCC28610 is facilitated by driving the external high voltage MOSFET through the source. This configuration is called a cascode driver. It features fast start-up and low input power under no-load conditions without having high voltage connections to the control device. The cascode driver has no effect on the general operation of the flyback converter.
The feedback pin uses current rather than voltage. This unique feature minimizes primary side power consumption during no-load operation by avoiding external resistive conversion from opto-coupler current to voltage.
Average efficiency is optimized by the UCC28610 between peak power and 22% peak power with constant peak current, variable off-time modulation. This modulation tends to make the efficiency constant between 22% and 100% peak load, eliminating the need to over-design to meet average efficiency levels that are required by EnergyStar™.
The UCC28610 reacts with the programmed overload response if the overload lasts longer than tOL (nominally 250 ms). The overload fault responses are either (1) latch-off or (2) shutdown/retry after a retry delay of 750 ms. The overload response is programmed with the MOT pin. The forced DCM feature prevents transformer saturation and limits the average and RMS output currents of the secondary winding of the transformer. Even under short circuit load conditions, the output current of the transformer is limited to the levels that are shown in Equation 1, where NPS is the primary-to-secondary turns ratio. Typical behavior for a shorted load is shown in Figure 18.
In shutdown/retry mode switching will be re-enabled after the 750-ms retry delay. In latch-off mode, a 7.5-kΩ load is activated at the DRV pin upon the activation by a fault condition. The internal 7.5-kΩ load draws current from the bulk capacitor through the HVMOSFET and the transformer primary winding. The bias voltage, VDD, is also regulated by the HVMOSFET during the latch-off state. Once the AC line is removed, a 2.8-mA current, IDRV,DSCH, will discharge the bulk capacitor. Ultimately, VDD will discharge when the bulk voltage becomes sufficiently low. A normal start-up cycle can occur if the input voltage is applied after VDD falls below the fault reset level, VDD(FAULT RESET), which is approximately equal to 6 V.
The forced DCM feature provides protection against excessive primary currents in the event that the input voltage becomes very low. The highest possible secondary currents can be described by Equation 1. The UCC28610 adds further protection by allowing the user to program the maximum on-time.
The Maximum On-Time (MOT) function causes the converter to react as if there is an overload condition if the load is sufficiently large during a line sag condition. During low line conditions the MOT function limits the on-time of the primary switch which limits the peak current in the primary power stage. Figure 19 shows how the MOT period, tMOT, is programmed over the range of 1.5 μs to 5 μs for either range of programming resistors. The resistor range determines the controller’s response to a sustained overload fault – to either Latch-off or to Shutdown/Retry, which is the same response for a line-sag, or brown out, condition.
Many applications require the ability to shutdown the power supply with external means. This feature is easily implemented by connecting the collector and emitter of an NPN transistor between MOT and GND, respectively. The NPN transistor can be the photo-transistor of an opto-isolator for isolated applications.
For latch-off response to over-current or brownout:
where:
For shut-down/retry response to over-current or brownout:
where:
The UCC28610 controller monitors the output voltage by sampling the voltage at the auxiliary winding. The sampling time has a fixed delay of 1 μs, tBLANK,OVP, after the internal driver turns off. This allows the auxiliary winding to be sampled after the bias winding voltage settles from the transient. This same delay is used to blank the ZCD input to avoid unintended zero crossing detection should the ringing be large enough to cross the ZCD zero crossing threshold.
The output over-voltage (OV) threshold is set using the turn ratio of the auxiliary winding to the output secondary and a resistive divider into the ZCD input pin. The UCC28610 will always enter a latched-off state if it detects an OV condition. The VDD supply must cycle below the fault reset threshold to re-start in order to recover. The functionality of the over-voltage detection function is shown in Figure 20.
Cascode drive circuits are well known for high speed voltage gain. This topology can have small signal bandwidth well over 100 MHz and it can exhibit high frequency ringing. The internal HS Drive MOSFET shorts the gate to source of the external HVMOSFET during the turn-off interval of the switch cycle. This prevents the HVMOSFET from undesirably exciting the LC resonant circuit in the converter (the magnetizing inductance of the transformer and the stray drain capacitance). High frequency ringing can appear within the built-in dead-time between the turn-off of DRV and the turn-on of the HS Drive. A large amount of energy is transferred through the power components during this dead-time. Excessive high frequency ringing can cause EMI problems and become destructive in some situations.
The high frequency ringing is the result of stray capacitances ringing with the stray inductance between the source of the HVMOSFET and the DRV pin. Low threshold voltage of the high voltage MOSFET and large peak DRV current can make the ringing worse. In destructive ringing situations, the converter may easily power up and attain regulation the first time, never to start-up again.
The ringing can be observed in either or both of the following conditions:
High frequency ringing problems with cascode MOSFET drives can often be avoided. Many converters will not have this problem because they use an HVMOSFET with a large Vth, large RDS(on), low transconductance gain, or operate at low current. Ringing problems can also be avoided by minimizing stray inductance. The trace between the HVMOSFET source and the DRV pin must be kept very short, less than 1 cm. Do not add current probe loops to the source lead of the HVMOSFET. Do not place ferrite beads on the source lead of the HVMOSFET.
If ringing cannot be avoided, the most efficient and effective methods to solve ringing during switching transients are:
The ferrite chip or bead connected to the gate of the HVMOSFET provides the best result because it suppresses ringing in the gate, source, and drain circuits of the HVMOSFET with minimal added losses. Select the ferrite chip for its resistance value in the ringing frequency range (for example, 60 Ω at 100 MHz). The peak current rating of the ferrite chip or bead must be sufficient for the drain – gate discharge current that occurs during the turn-off transient. Excessively large bead reactance can result in low frequency surges of VGG at peak load. Normally, good results can be achieved with a 0603 ferrite chip device.
A capacitor between DRV and GND can reduce ringing on VGG. Select the DRV capacitor experimentally by observing the effect on the VGG pin during the first turn-off edge and during the turn-off edge at full load operation. The capacitor should be less than 3.3 nF so that it does not significantly reduce efficiency. Use a capacitor with a low Q, such as one with Y5V dielectric. This technique will not completely damp the ringing yet it can provide sufficient protection against stray inductance between the source of the HVMOSFET and the DRV pin.
A gate turn-off resistor in the range 0 Ω < RG-OFF < 5 Ω can damp ringing. The turn-off resistance is limited in order to prevent the stray source inductance of the HVMOSFET from over charging VGG through the body diode of the HS Drive MOSFET, in addition to any peak current error problems that would be caused by additional delay. The damping effect of the gate resistor works better in applications with low current and small source inductance.
A much larger resistance can be tolerated during the HVMOSFET turn-on transition due to DCM operation. The recommended turn-on resistance range is 0 Ω <RG-ON < 200 Ω in order to prevent the turn-on delay from interfering with valley switching.
The UCC28610 protects itself from overheating with an internal thermal shutdown circuit. If the junction temperature exceeds the thermal shutdown point, TSD, the UCC28610 initiates a shutdown event and permits retry after the retry time, tRETRY. Shutdown/Retry cycles continue if the junction temperature is not less than TSD minus TSD_HYST.
According to the voltage and current among IC pins and the input voltage, output loading conditions, UCC28610 operates in different functional modes.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
To begin a power supply design, the power supply designer needs to know the peak power to be delivered by the converter, the input voltage range, the output voltage, and an estimate of the maximum allowable bulk voltage ripple. Select the maximum allowable stress voltage for the external power MOSFET. The stress voltage, VDS, determines the reflected secondary voltage that resets the flyback transformer and the turn ratio between primary and secondary. A simplified diagram of the converter and its waveforms are shown in Figure 22.
Peak power is the maximum power level that must be regulated by the converter control system. Loads that last longer than the control loop time constant (100 μs - 300 μs) are directly considered “peak power”. Loads lasting less than the control loop time constant can be averaged over the control loop time constant.
The minimum switching period is when the converter is operating in the Frequency Modulation (FM) mode, referred to as tS(HF). This switching period must equal the sum of the switching intervals at minimum input voltage, maximum load, as shown in Figure 22 and described in Equation 6. The switching intervals are tON, the conduction time of the MOSFET; tDM the demagnetization time of the transformer and tDT, the duration of the deadtime, equal to half of the resonant cycle, after the transformer is de-energized.
Solve for the primary to secondary turn ratio, NPS, using the maximum allowable VDS, the maximum input line voltage, the predicted voltage spike due to leakage inductance and the desired regulated output voltage of the converter, VOUT.
Assume a deadtime, tDT, of 5% of the total minimum switching period to allow for variations in the output capacitance of the HVMOSFET and the leakage inductance value:
Using volt-seconds balance, set the volt-seconds on equal to the volt-seconds for demagnetizing and solve for the on-time:
The maximum input power, PIN, to the converter, in addition to being equal to the output power divided by the overall efficiency, is always equal to:
Solve for the primary inductance value:
This equation is an approximation of the primary inductance value that is the best choice to minimize the primary side RMS current. In the actual circuit, when the resonance and delay due to leakage inductance can be measured, the magnetizing inductance value may need to be iterated for optimized low voltage switching.
Select the CL resistor, RCL, based upon the maximum power constant of the controller, KP, The tolerance of LM should be considered (such as 10% lower for a typical inductor) and the minimum value of LM should be used to calculate the value of the CL resistor.
To avoid tripping the overload protection feature of the controller during the normal operating range, use the minimum value of KP from the Electrical Characteristics Table:
Once RCL is selected, the peak DRV current is calculated using Equation 10:
For high efficiency, the bias winding turn ratio, NPB, should be designed to maintain the VDD voltage above the VGG clamp, which is equal to VGG(DISABLED), when the converter is in burst mode. If VDD discharges below this value, minus the threshold voltage of the HVMOSFET, the HVMOSFET will turn on and linearly supply the VDD current from the high voltage rail instead of from the bias windings. Adding a zener diode on VDD will protect VDD from exceeding its absolute maximum rating in the event of a spike due to excess leakage inductance.
The UCC28610 uses a cascode drive and bias to control the high voltage power MOSFET and provide initial bias at start-up. Thus, the external high voltage power MOSFET provides the start-up function in addition to the power switching function during converter operation. The cascode architecture utilizes a low voltage switch operating between ground and the source of a high voltage MOSFET (HVMOSFET) configured in a common gate configuration, as shown in Figure 23. There are some key points to note.
The UCC28610 integrates the low voltage switch in the form of a 90-mΩ FET along with all associated current sensing and drive. The HVMOSFET is forced to track the fast internal low voltage driver. The drain-gate charge in the HVMOSFET does not affect the turn-off speed because the gate is connected to a low impedance DC source. The cascode configuration results in very fast turn-off of the HVMOSFET, which keeps MOSFET switching losses low.
Cascode drive circuits are well known for high speed voltage gain. This topology can have small signal bandwidth over 100 MHz and it can exhibit high frequency ringing. High frequency ringing can cause EMI problems and become destructive in some situations. The sub-intervals during and immediately following the turn-on and turn-off transients are particularly susceptible to oscillation. For avoidance or solutions, see the application section, Solving High Frequency Ringing.
The cascode configuration permits a unique start-up sequence that is fast yet low-loss. Start-up bias uses a low level bleed current from either the AC line or the rectified and filtered AC line, or bulk voltage (via RSTART) as shown in Figure 24. This current charges a small VGG capacitor, CVGG, raising the HVMOSFET gate. The VGG pin will typically draw approximately 6 μA (IVGG(SREG)) during this time, allowing the bulk bias current to be small and still charge the VGG capacitor. The HVMOSFET acts as a source follower once VGG reaches the threshold voltage of the HVMOSFET. Then, the HVMOSFET will bring up the DRV voltage as VGG continues to rise. During this time the UCC28610 is in UVLO and the Enable PWM signal is low. This turns on the VDD switch connecting VDD to DRV, allowing VDD to rise with the source of the HVMOSFET and charging CVDD. An external Schottky diode, D1, is required between DRV and VDD. This diode passes potentially high switching currents that could otherwise flow through the body diode of the internal VDD Switch.
In order to achieve the lowest possible no-load power, select the number of turns in the bias winding so that VDD is higher than 16 V – VTH of the HVMOSFET. A bias winding voltage between 17 V and 20 V usually achieves minimum loss. The bias winding often tracks the primary leakage inductance turn-off voltage spike. Place a 20-V Zener diode between VDD and GND in applications where heavy loads cause excessive VDD voltage.
Typical start-up waveforms are shown in Figure 25. As VGG rises, VDD will follow, minus the threshold voltage of the HVMOSFET. When VDD reaches approximately 10 V, the UCC28610 initiates switching. The bias supply current, IVDD, rises to its operating level and it is supplied from the VDD capacitor. Start-up times can be kept under 200 ms by selecting the VGG capacitor in the range of 33 nF to 1000 nF and selecting RSTART to have a current of 15 μA at the minimum AC line voltage. Select capacitor CVDD to have enough capacitance to provide operating bias current to the controller for the time it takes the auxiliary winding to take over. No-load burst operation may impose a requirement for additional CVDD capacitance.
The voltage on VGG is shunt regulated to 16 V whenever the PWM action is disabled. This is reduced to 14 V during switching to limit voltage stress on the gate of the external HVMOSFET. The external HVMOSFET should have a threshold voltage of less than 6 V in order to permit proper starting.
Modulation and modes are controlled by applying current to the FB pin. The FB pin is usually used to feed back the output error signal to the modulator. The UCC28610 uses internal current mirrors to apply the FB current to the Feedback Processing block, and then to the Frequency Modulator and Current Modulator blocks. The voltage of the FB pin is a constant 0.7 V. AC filtering of the output of the opto-coupler must be applied at the FB pin, as shown in Figure 26. The corner frequency of the filter in Figure 26 should be at least a decade above the maximum switching frequency of the converter, as given in Equation 16. A 100-kΩ resistor, RFB, between the opto-coupler emitter and GND prevents ground noise from resetting the overload timer by biasing the FB pin with a negative current. An opto-coupler with a low Current Transfer Ratio (CTR) is required to give better no-load performance than a high CTR device due to the bias current of the secondary reference. The low CTR also offers better noise immunity than a high CTR device.
Under normal operating conditions, the FB current commands the operating mode of the UCC28610, as shown in Figure 27 and Figure 28. The FB current commands the UCC28610 to operate the converter in one of three modes: Frequency Modulation (FM) mode, Amplitude Modulation (AM) mode, and Green Mode (GM).
The converter operates in FM mode with a large power load (22% to 100% the peak regulated power). The peak HVMOSFET current reaches its maximum programmed value and FB current regulates the output voltage by varying the switching frequency, which is inversely proportional to tS. The switching frequency is modulated from 30 kHz (22% peak power) to 133 kHz (100% peak power), the on time is constant, and the IDRV peak current is constant. The maximum programmable HVMOSFET current, IDRV,PK(max), is set by a resistor on the CL pin, as described in Equation 15.
The converter operates in AM mode at moderate power levels (2.5% to 22% of the peak regulated power). The FB current regulates the output voltage by modulating the amplitude of the peak HVMOSFET current from 33% to 100% of the maximum programmed value while the switching frequency is fixed at approximately 30 kHz. The UCC28610 modulates the voltage on the CL pin from 3 V to 1 V to vary the commanded peak current, as shown in Figure 27 and Figure 28.
The converter operates in GM at light load (0% to 2.5% of the peak regulated power). The FB current regulates the output voltage in the Green Mode with hysteretic bursts of pulses using FB current thresholds. The peak HVMOSFET current is 33% of the maximum programmed value. The switching frequency within a burst of pulses is approximately 30 kHz. The duration between bursts is regulated by the power supply control dynamics and the FB hysteresis. The UCC28610 reduces internal bias power between bursts in order to conserve energy during light-load and no-load conditions.
The UCC28610 uses a current mirror technique to sense primary current in the Current Modulator. See Figure 29 for details. All of the primary current passes into the DRV pin, through the Driver MOSFET and out of the GND pin. The Driver MOSFET current is scaled and reflected to the PWM Comparator where it is compared with the CL current. At the beginning of each switching cycle a blanking pulse, tBLANK,(Ilim), of approximately 220 ns is applied to the internal current limiter to allow the driver to turn on without false limiting on the leading edge capacitive discharge currents normally present in the circuit.
The modulator requires three conditions in order to initiate the next switching cycle:
Every switching cycle is preceded by at least one zero crossing detection by the ZCD pin. The modulator allows the resonant ring to damp between pulses if the period needs to exceed the damping limit, allowing long pauses between pulses during no-load operation.
The switching frequency is not allowed to exceed 133 kHz (nominally). This sets the maximum power limit so that it will be constant for all bulk voltages that exceed the minimum line voltage value.
Figure 30 illustrates a set of switching cycle waveforms over a range of operating conditions. The UCC28610 is designed to always keep the inductor current discontinuous. This prevents current tailing during start-up or short circuit conditions and accommodates control of the maximum power delivered.
Zero crossing is detected using a resistive divider across the bias winding, as shown in Figure 31. The bias winding operates in phase with the output winding. The ZCD function detects transformer demagnetization when the ZCD voltage has a high to low crossing of the 20-mV ZCD threshold, ZCDTH. The voltage at the ZCD pin is internally clamped to contain negative excursions at -160mV (ZCDCLAMP). A small delay, 50 ns to 200 ns, can be added with CZCD to align the turn-on of the primary switch with the resonant valley of the primary winding waveform.
During light load operation the UCC28610 cycles between two states: GM-on and GM-off. The details are shown in Figure 32. During the GM-on state, the controller is active while the modulator issues a burst of one or more pulses. During the GM-off state the controller reduces its operating current and switching action is inhibited. The rate and duration of the on and off states are controlled by the current into the FB pin as it cycles between the two hysteretic thresholds separated by IFB, GM_HYST, the load current, the output filter capacitor, and the details of the feedback circuit.
During the GM-off state the VDD supply current is reduced to approximately 550 μA, IVDD(GM). The Enable PWM signal goes low which inhibits switching, sets the VGG shunt regulation to ~16 V, VGG(DISABLED), and turns on the VDD switch. The VGG node quickly charges to 16V and the low VDD current is supplied from the VDD capacitor.
During the GM-on state the UCC28610 controls the peak primary current to 33% of IDRV,PK(max), at a 30-kHz rate. When switching, the VGG shunt regulator pulls the VGG voltage down to ~14 V. VDD is charged by the auxiliary winding during this time as long as VDD does not discharge below 14 V. The converter’s output voltage is charged until the feedback network forces the FB current to the GM off threshold, IFB,CNR3, and puts the controller back into the GM off state.
At very light loads the time between PWM bursts can be long. To obtain the lowest no-load power, it is important that VDD not discharge below 16 V by more than the threshold voltage of the HVMOSFET or the HVMOSFET will turn-on and linearly supply the VDD current from the high-voltage bulk rail. The VDD voltage can be extended by increasing the CVDD capacitance without significant impact on start-up time.
The suggested peak power range of the UCC28610 is 12 W to 65 W based on a universal AC line converter (90-VAC to 265-VAC input line voltage), using an external high voltage MOSFET with a voltage rating of 600 V. This power range may depend on application and external MOSFET stress voltage. Ultimately, the peak primary current is the limiting factor because this current must pass through the UCC28610. The limit on the peak primary current imposes a limit on the peak primary power. The peak power must be less than 65 W, not the average power. The peak power is defined as the highest power level where the controller must maintain regulation.
At all power levels, program the UCC28610 to control the power limit with the primary inductance, peak current and maximum switching frequency (133 kHz). The maximum peak input power level is given by Equation 19. The accuracy of the power limit is twice as sensitive to IDRV(PK) errors than LM errors and fS(max) errors. If the load demands more power than the programmed level, the power supply output voltage sags and the overload timer is initiated.
The dynamics of the DRV current sense imposes the 12-W minimum power level limit for this controller. The power level limits are found from DRV current estimates for typical universal AC adapters that use a 600-V MOSFET. The power range and its associated peak current range are given in Equation 20.
The minimum power level is due to a loss of linearity of the current mirror, as shown in Figure 33. A programmed IDRV,PK level between 0.66 A and 1 A (by using 100 kΩ ≤ RCL ≤ 150 kΩ) allows only a 2:1 amplitude modulation range of the peak DRV current. The amplitude of IDRV modulates linearly if IDRV,PK is programmed within its recommended operating range (1.0 A < IDRV,PK < 4.1 A, corresponding to 100 kΩ > RCL > 24.3 kΩ respectively.
Table 1 illustrates a typical subset of high-level design requirements. Many of these parameter values are used in the design equations contained in Table 2.
PARAMETER | CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERISTICS | ||||||
VIN | Input voltage | 85 | 265 | VRMS | ||
OUTPUT CHARACTERISTICS | ||||||
VOUT | Output voltage | VIN = min to max, IOUT = min to max | 10.8 | 12 | 13.2 | V |
Vripple | Output voltage ripple | VIN = 115 VRMS, IOUT = max | 80 | 120 | mVpp | |
IOUT | Output current | VIN = min to max | 0 | 2.1 | A | |
IOCP | Output over current inception point | VIN = max | 3 | A | ||
VOVP | Output OVP | IOUT = min to max | 16 | V | ||
Transient response voltage over shoot | IOUT = min to max | 500 | mV | |||
SYSTEM CHARACTERISTICS | ||||||
hPEAK | Peak efficiency | VIN = 115 VRMS, IOUT = 1.05 A | 85.7% | |||
No load power consumption | VIN = 115 VRMS | 67 | mW | |||
VIN = 230 VRMS | 107 |
For reference designators refer to Figure 34.
NAME | PIN | DESCRIPTION |
---|---|---|
CL | 3 | ![]() |
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Where KP = 0.54W/ μH | ||
LM is the minimum value of the primary inductance | ||
PIN = POUT/η | ||
η = efficiency | ||
DRV | 6 | Q1, power MOSFET with adequate voltage and current ratings, VVGS must have at least 20-V static rating. |
D1, Schottky diode, rated for at least 30 V, placed between DRV and VDD | ||
FB | 1 | RFB = 100 kΩ |
GND | 7 | Bypass capacitor to VDD, CBP = 0.1-μF, ceramic |
MOT | 4 | For latch-off response to overcurrent faults: |
tMOT = user programmable maximum on-time after 250-ms delay. | ||
![]() where
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For shutdown-retry response to overcurrent faults: | ||
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VDD | 8 | ![]() |
where: | ||
ΔVDD(BURST) is the allowed VDD ripple during burst operation | ||
tBURST is the estimated burst period, | ||
The typical CVDD value is approximately 47 μF | ||
DBIAS must have a voltage rating greater than: | ||
![]() |
||
where: | ||
VDBIAS is the reverse voltage rating of diode D2 | ||
VBULK(max) is the maximum rectified voltage of CBULK at the highest line voltage | ||
VGG | 5 | minimize the length of the CVGG connection to GND |
CVGG = at least 10x CGS of HVMOSFET, usually | ||
CVGG = 0.1 μF. | ||
ZCD | 2 | ![]() ![]() |
where: | ||
ZCD(ovp) is the overvoltage fault threshold at ZCD | ||
NPS is the primary to secondary turns ratio | ||
NPB is the primary to bias turns ratio | ||
VOUT is the average output voltage of the secondary | ||
VF is the forward bias voltage of the secondary rectifier | ||
VOUT,PEAK is the desired output overvoltage fault level |
Bulk capacitance may consist of one or more capacitors connected in parallel. The input power of the converter based on target full-load efficiency, minimum input RMS voltage, minimum AC input frequency, and minimum bulk capacitor voltage are used to determine the bulk capacitor value. Maximum input power is used in the CBULK calculation and is determined by:
Assume 30% voltage ripple on the bulk capacitor, the minimum bulk capacitor voltage is 70% of the minimum input AC voltage at its peak value.
Equation 23 provides an accurate solution for input capacitance needed to achieve a minimum bulk valley voltage target VBULK(min), accounting for hold-up during any loss of AC power for a certain number of half cycles, NHC, by an AC-line drop-out condition. Alternatively, if a given input capacitance value is prescribed, iterate the VBULK(min) value until that target capacitance is obtained, which determines the VBULK(min) expected for that capacitance.
To begin a power supply design, the power supply designer needs to know the peak power to be delivered by the converter, the input voltage range, the output voltage, and an estimate of the maximum allowable bulk voltage ripple. Select the maximum allowable stress voltage for the external power MOSFET. The stress voltage, VDS, determines the reflected secondary voltage that resets the flyback transformer and the turn ratio between primary and secondary. A simplified diagram of the converter and its waveforms are shown in Figure 22.
Peak power is the maximum power level that must be regulated by the converter control system. Loads that last longer than the control loop time constant (100 μs - 300 μs) are directly considered “peak power”. Loads lasting less than the control loop time constant can be averaged over the control loop time constant.
The minimum switching period is when the converter is operating in the Frequency Modulation (FM) mode, referred to as tS(HF). This switching period must equal the sum of the switching intervals at minimum input voltage, maximum load, as shown in Figure 35 and described in Equation 24. The switching intervals are tON, the conduction time of the MOSFET; tDM the demagnetization time of the transformer and tDT, the duration of the deadtime, equal to half of the resonant cycle, after the transformer is de-energized.
Solve for the primary to secondary turn ratio, NPS, using the maximum allowable VDS, the maximum input line voltage, the predicted voltage spike due to leakage inductance and the desired regulated output voltage of the converter, VOUT.
Assume a deadtime, tDT, of 5% of the total minimum switching period to allow for variations in the output capacitance of the HVMOSFET and the leakage inductance value:
Using volt-seconds balance, set the volt-seconds on equal to the volt-seconds for demagnetizing and solve for the on-time:
The maximum input power, PIN, to the converter, in addition to being equal to the output power divided by the overall efficiency, is always equal to:
Solve for the primary inductance value:
This equation is an approximation of the primary inductance value that is the best choice to minimize the primary side RMS current. In the actual circuit, when the resonance and delay due to leakage inductance can be measured, the magnetizing inductance value may need to be iterated for optimized low voltage switching.
Select the CL resistor, RCL, based upon the maximum power constant of the controller, KP, The tolerance of LM should be considered (such as 10% lower for a typical inductor) and the minimum value of LM should be used to calculate the value of the CL resistor.
To avoid tripping the overload protection feature of the controller during the normal operating range, use the minimum value of KP from the Electrical Characteristics Table:
Once RCL is selected, the peak DRV current is calculated using Equation 10:
For high efficiency, the bias winding turn ratio, NPB, should be designed to maintain the VDD voltage above the VGG clamp, which is equal to VGG(DISABLED), when the converter is in burst mode. If VDD discharges below this value, minus the threshold voltage of the HVMOSFET, the HVMOSFET will turn on and linearly supply the VDD current from the high voltage rail instead of from the bias windings. Adding a zener diode on VDD will protect VDD from exceeding its absolute maximum rating in the event of a spike due to excess leakage inductance.
Modulation and modes are controlled by applying current to the FB pin. The FB pin is usually used to feed back the output error signal to the modulator. The UCC28610 uses internal current mirrors to apply the FB current to the Feedback Processing block, and then to the Frequency Modulator and Current Modulator blocks. The voltage of the FB pin is a constant 0.7 V. AC filtering of the output of the opto-coupler must be applied at the FB pin, as shown in Figure 36. The corner frequency of the filter in Figure 36 should be at least a decade above the maximum switching frequency of the converter, as given in Equation 34. A 100-kΩ resistor, RFB, between the opto-coupler emitter and GND prevents ground noise from resetting the overload timer by biasing the FB pin with a negative current. An opto-coupler with a low Current Transfer Ratio (CTR) is required to give better no-load performance than a high CTR device due to the bias current of the secondary reference. The low CTR also offers better noise immunity than a high CTR device.
Zero crossing is detected using a resistive divider across the bias winding, as shown in Figure 37. The bias winding operates in phase with the output winding. The ZCD function detects transformer demagnetization when the ZCD voltage has a high to low crossing of the 20-mV ZCD threshold, ZCDTH. The voltage at the ZCD pin is internally clamped to contain negative excursions at -160mV (ZCDCLAMP). A small delay, 50 ns to 200 ns, can be added with CZCD to align the turn-on of the primary switch with the resonant valley of the primary winding waveform.
The UCC28610 VDD can be charged through high-voltage MOSFET directly from the high-voltage bus at startup. Due to the nature of high loss, this charging path is intended for startup operation only. During normal operation, the VDD voltage should be high enough to avoid this high-loss charging path.
In order to achieve the lowest possible no-load power, select the number of turns in the bias winding so that VDD is higher than 16V-VTH of the high voltage MOSFET. A bias winding voltage between 17 V and 20 V usually achieves minimum loss. The bias winding often tracks the primary leakage inductance turn-off voltage spike. Place a 20-V Zener diode between VDD and GND in applications where the heavy loads cause excessive VDD voltage.