SLUS987C January 2011 – December 2019 BQ33100
PRODUCTION DATA.
The BQ33100 can monitor two, three, four, or five capacitors in series. Table 1 shows the appropriate connectivity for the different options.
BQ33100 PIN | 5-SERIES | 4-SERIES | 3-SERIES | 2-SERIES |
---|---|---|---|---|
VC1 | P of Top (5th) Cap | P of 4th Cap | Short to VC2 | Short to VC2 |
VC2 | P of 4th Cap, N of 5th Cap | P of 3rd Cap, N of 4th Cap | P of 3rd Cap | Short to VC3 |
VC3 | P of 3rd Cap, N of 4th Cap | P of 2nd Cap, N of 3rd Cap | P of 2nd Cap, N of 3rd Cap | P of 2nd Cap |
VC4 | P of 2nd Cap, N of 3rd Cap | P of Bottom (1st) Cap, N of 2nd Cap | P of Bottom (1st) Cap, N of 2nd Cap | P of Bottom (1st) Cap, N of 2nd Cap |
VC5 | P of Bottom (1st) Cap, N of 2nd Cap | N of Bottom Cap (1st) | N of Bottom Cap (1st) | N of Bottom Cap (1st) |
VSS | N of Bottom Cap (1st) | Short to VC5 | Short to VC5 | Short to VC5 |
SPACE
NOTE
The CC0...CC2 bits in Operation Cfg must be programmed to match the corresponding configuration.
When in STACK mode (Operation Cfg [STACK] =1), VC1 must be connected to VC2 and VC3 connected to VC4. Additionally, a divide-by-2 resistor divider must connect between the top and bottom of the capacitor array with VC1,2 being the top, VC3,4 being the middle, and VSS being the bottom. In this configuration, pins VC5 and VC5BAL are not used and must be connected to VSS.