SLUSAF2C February   2011  – April 2015

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Battery Voltage Regulation
      2. 9.3.2  Battery Current Regulation
      3. 9.3.3  Battery Precharge Current Regulation
      4. 9.3.4  Input Current Regulation
      5. 9.3.5  Charge Termination, Recharge, and Safety Timers
      6. 9.3.6  Power Up
      7. 9.3.7  Input Undervoltage Lockout (UVLO)
      8. 9.3.8  Input Overvoltage/Undervoltage Protection
      9. 9.3.9  Enable and Disable Charging
      10. 9.3.10 System Power Selector
      11. 9.3.11 Converter Operation
      12. 9.3.12 Automatic Internal Soft-Start Charger Current
      13. 9.3.13 Charge Overcurrent Protection
      14. 9.3.14 Charge Undercurrent Protection
      15. 9.3.15 Battery Detection
        1. 9.3.15.1 Example
      16. 9.3.16 Battery Short Protection
      17. 9.3.17 Battery Overvoltage Protection
      18. 9.3.18 Temperature Qualification and JEITA Guideline
      19. 9.3.19 MOSFET Short Circuit and Inductor Short Circuit Protection
      20. 9.3.20 Thermal Regulation and Shutdown Protection
      21. 9.3.21 Timer Fault Recovery
      22. 9.3.22 Inductor, Capacitor, and Sense Resistor Selection Guidelines
      23. 9.3.23 Charge Status Outputs
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
        4. 10.2.2.4 Input Filter Design
        5. 10.2.2.5 Input ACFET and RBFET Selection
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

12 Layout

12.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize the high-frequency current path loop (see Figure 24) is important to prevent electrical and magnetic field radiation and high-frequency resonant problems. The following is a PCB layout priority list for proper layout. Layout of the PCB according to this specific order is essential.

  1. Place the input capacitor as close as possible to the PVCC supply and ground connections and use the shortest copper trace connection. These parts should be placed on the same layer of the PCB instead of on different layers and using vias to make this connection.
  2. Place the inductor input terminal as close as possible to the SW terminal. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  3. The charging current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in the same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection for best current accuracy). Place decoupling capacitor on these traces next to the IC.
  4. Place the output capacitor next to the sensing resistor output and ground.
  5. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground.
  6. Route analog ground separately from power ground and use a single ground connection to tie charger power ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. Use the thermal pad as a single ground connection point to connect analog ground and power ground together, or use a 0-Ω resistor to tie analog ground to power ground. A star-connection under the thermal pad is highly recommended.
  7. It is critical to solder the exposed thermal pad on the backside of the IC package to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
  8. Decoupling capacitors must be placed next to the IC pins and make trace connection as short as possible.
  9. The number and physical size of the vias must be enough for a given current path.

12.2 Layout Example

bq24171 hi_f_path_lusa75.gifFigure 24. High-Frequency Current Path
bq24171 sens_res_layout_lusad2.gifFigure 25. Sensing Resistor PCB Layout