SLUSAP5A December   2011  – November 2016 TPS53316

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overcurrent and Frequency Setting
      2. 7.3.2 Soft-Start Operation
      3. 7.3.3 Power Good
      4. 7.3.4 UVLO Function
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 Undervoltage Protection
      8. 7.3.8 Overtemperature Protection
      9. 7.3.9 Output Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Determine the Value of R1 and R2
        2. 8.2.2.2 Choose the Inductor
        3. 8.2.2.3 Choose the Output Capacitor(s)
        4. 8.2.2.4 Choose the Input Capacitors
        5. 8.2.2.5 Compensation Design
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN –0.3 7 V
VBST –0.3 17
VBST (with respect to LL) –0.3 7
EN –0.3 7
FB, PS, RF/OC –0.3 3.7
Output voltage SW DC –1 7 V
Pulse < 20 ns, E = 5 µJ ≥–5 <10
PGD –0.3 7
COMP, VREG3 –0.3 3.7
PGND –0.3 0.3
Junction temperature, TJ –40 150 °C
Operating open-air temperature, TA –40 85 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
Input voltage VIN (main supply) 2.9 6 V
VBST –0.1 13.5
VBST (with respect to SW) –0.1 6
EN, –0.1 6
FB, PS, RF/OC –0.1 3.5
Output voltage SW –1 6.5 V
PGD –0.1 6
COMP, VREG3 –0.1 3.5
PGND –0.1 0.1
TJ Junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS53316 UNIT
RGT (QFN)
16 PINS
RθJA Junction-to-ambient thermal resistance 45.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54.3 °C/W
RθJB Junction-to-board thermal resistance 18.3 °C/W
ψJT Junction-to-top characterization parameter 1.1 °C/W
ψJB Junction-to-board characterization parameter 18.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range, VIN = 3.3 V, PGND = GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY: VOLTAGE, CURRENTS, AND UVLO
VVIN VIN supply voltage Nominal input voltage range 2.9 6 V
IVIN(sdn) VIN shutdown current EN = LO 15 µA
IVIN VIN supply current EN = HI, VFB = 0.63 V, No load 2 3.5 mA
VUVLO VIN UVLO threshold Ramp up, EN = HI 2.8 V
VUVLO(hys) VIN UVLO hysteresis VIN UVLO hysteresis 120 mV
VREG3 LDO output VVIN = 5 V, 0 ≤ IDD ≤ 5 mA 3.135 3.3 3.465 V
VOLTAGE FEEDBACK LOOP: VREF AND ERROR AMPLIFIER
VVREF VREF Internal precision reference voltage 0.6 V
TOLVREF VREF tolerance 0°C ≤ TA≤ 85°C –1% 1%
–40°C ≤ TA≤ 85°C –1.25% 1.25%
UGBW(1) Unity gain bandwidth 14 MHz
AOL(1) Open-loop gain 80 dB
IFBINT FB input leakage current Sourced from FB pin 30 nA
IEA(max)(1) Output sinking and sourcing current CCOMP = 20 pF 5 mA
SR(1) Slew rate 5 V/µs
OCP: OVERCURRENT AND ZERO CROSSING
IOCPL3A(4) Overcurrent limit on high-side FET 4.5-A setting, when IOUT exceeds this threshold for 4 consecutive cycles,
VVIN = 3.3 V, VOUT = 1.5 V with 1-µH inductor, fSW = 1.1 MHz, TA= 25°C		 4.05 4.5 4.95 A
IOCPH3A(4) One-time overcurrent latch off on the low-side FET 4.5-A setting, immediate shuts down when sensed current reach this value
VVIN = 3.3 V, VOUT = 0.6 V with 1-µH inductor, fSW = 1.1 MHz, TA= 25°C		 4.49 5.1 5.61 A
IOCPL5A(4) Overcurrent limit on high-side FET 6.5-A setting, when IOUT exceeds this threshold for 4 consecutive cycles,
VVIN = 3.3 V, VOUT = 1.5 V with 1-µH inductor, fSW = 1.1 MHz, TA= 25°C 		6.1 6.8 7.5 A
IOCPH5A(4) One time overcurrent latch off on the low-side FET 6.5-A setting, immediate shut down when sensed current reaches this value
VVIN = 3.3 V, VOUT = 0.6 V with 1-µH inductor, fSW = 1.1 MHz, TA= 25°C 		6.75 7.5 8.3 A
thiccup Hiccup time interval fSW = 1.1 MHz 14.5 ms
VZXOFF(1) Zero crossing comparator internal offset PGND – SW, SKIP mode –4.5 –3 –1.5 mV
PROTECTION: OVP, UVP, PGD, AND INTERNAL THERMAL SHUTDOWN
VOVP Overvoltage protection threshold voltage Measured at the FB w/r/t VREF 114% 117% 120%
VUVP Undervoltage protection Threshold voltage Measured at the FB w/r/t VREF 80% 83% 86%
VPGDL PGD low threshold Measured at the FB w/r/t VREF 80% 83% 86%
VPGDU PGD upper threshold Measured at the FB w/r/t VREF 114% 117% 120%
VINMINPG Minimum input voltage for valid PGD at start-up Measured at VIN with 1-mA sink current on PGD pin at start-up 1 V
THSD(1) Thermal shutdown 130 140 150 °C
THSDHYS(1) Thermal shutdown hysteresis Controller start again after temperature has dropped 40 °C
LOGIC PINS: I/O VOLTAGE AND CURRENT
VPGPD PGD pull-down voltage Pulldown voltage with 4-mA sink current 0.1 0.3 V
IPGLK PGD leakage current Hi-Z leakage current, Apply 3.3 V in off state –2 0 2 µA
RENPU Enable pullup resistor 2.25 MΩ
VENH EN logic high VVIN = 3.3 V 0.82 0.97 1.1 V
VVIN = 5 V 0.95 1.1 1.25 V
VENHYS EN hysteresis VVIN = 3.3 V 0.16 0.24 V
VVIN = 5 V 0.2 0.275 V
PSTHS PS mode threshold voltage Level 1 to level 2(2) 0.12 V
Level 2 to level 3 0.4
Level 3 to level 4 0.8
Level 4 to level 5 1.4
Level 5 to level 6 2.2
IPS PS source 10-µA pull-up current when enabled 8 10 12 µA
RF/OCTHS RF/OC pin threshold voltage Level 1 to level 2(3) 0.12 V
Level 2 to level 3 0.4
Level 3 to level 4 0.8
Level 4 to level 5 1.4
Level 5 to level 6 2.2
IRF/OC RF/OC source current 10-µA pullup current when enabled 8 10 12 µA
BOOT STRAP: VOLTAGE AND LEAKAGE CURRENT
IVBSTLK VBST leakage current VVIN = 3.3 V, VVBST = 6.6 V, TA = 25°C 1 µA
TIMERS: SS, FREQUENCY, RAMP, ON-TIME AND I/O TIMING
tSS_1 Delay after EN Asserting EN = ‘HI’ 0.2 ms
tSS_2 Soft-start ramp_up time 0 V ≤ VSS ≤ 0.6 V 0.4 ms
0 V ≤ VSS ≤ 0.6 V, 4 x SS time (option2) 1.6
tPGDENDLY PGD start-up delay time VSS = 0.6 V to PGD (SSOK) going high 0.3 ms
VSS = 0.6 V to PGD (SSOK), option 2 1.2
tOVPDLY OVP delay time Time from FB out of +20% of VREF to OVP fault 1 1.7 2.5 µs
tUVPDLY UVP delay time Time from FB out of –20% of VREF to UVP fault 10 µs
fSW Switching frequency All modes, fSET = 0.75 MHz 0.653 0.725 0.798 MHz
All modes, fSET = 1.1 MHz 0.99 1.1 1.21
FCCM and DE mode, fSET = 2 MHz 1.71 1.9 2.09
HEF mode, fSET = 2 MHz 1.566 1.8 2.034 MHz
Ramp amplitude(1) 2.9 V ≤ VVIN ≤ 6 V VVIN/4 V
tMIN(off) Minimum OFF time, FCCM and DE All frequencies 90 130 ns
Minimum OFF time, HEF fSW = 1.1 MHz 160 240 ns
DMAX Maximum duty cycle, FCCM and DE fSW = 1.1 MHz 84% 89%
DMAX Maximum duty cycle, HEF All frequencies 75% 81%
RSFTSTP Soft-discharge transistor resistance EN = LO, VVIN = 3.3 V, VOUT = 0.5 V 60 Ω
(1) Ensured by design. Not production tested.
(2) See PS pin description for levels.
(3) See RF/OC pin description for levels.
(4) See Figure 5 and Figure 6 on OCP level for other operating conditions.

6.6 Typical Characteristics

Inductor used: PCMC065T-1R0, 1 µH, 5.6 mΩ
TPS53316 G017.png Figure 1. Reference Voltage vs Temperature
TPS53316 G019.png Figure 3. Output Voltage vs Output Current
TPS53316 G021.png Figure 5. OCP Threshold vs Output Voltage
TPS53316 G001.png Figure 7. Frequency vs Output Current, FCCM
TPS53316 G003.png Figure 9. Frequency vs Output Current, HEF Mode
TPS53316 G005.png Figure 11. Frequency vs Output Current, DE Mode
TPS53316 G007.png Figure 13. Efficiency vs Output Current, FCCM
TPS53316 G009.png Figure 15. Efficiency vs Output Current, HEF Mode
TPS53316 G011.png Figure 17. Efficiency vs Output Current, DE Mode
TPS53316 G013.png Figure 19. Efficiency vs Output Current, FCCM
TPS53316 G015.png Figure 21. Efficiency vs Output Current, FCCM
TPS53316 wave01_lusap5.gif Figure 23. Normal Start-up
TPS53316 wave03_lusap5.gif Figure 25. Turnoff Enable
TPS53316 wave05_lusap5.gif Figure 27. Output Voltage Ripple – FCCM
TPS53316 wave07_lusap5.gif Figure 29. Load Transient – FCCM
TPS53316 wave12_lusap5.gif Figure 31. DE Mode DCM and CCM Transition
TPS53316 wave09_lusap5.gif Figure 33. Overcurrent Protection
TPS53316 wave11_lusap5.gif Figure 35. Overtemperature Protection
TPS53316 G018.png Figure 2. Input Current vs Temperature
TPS53316 G020.png Figure 4. Output Voltage vs Input Voltage
TPS53316 G022.png Figure 6. OCP Threshold vs Output Voltage
TPS53316 G002.png Figure 8. Frequency vs Output Current, DE Mode
TPS53316 G004.png Figure 10. Frequency vs Output Current, FCCM
TPS53316 G006.png Figure 12. Frequency vs Output Current, HEF Mode
TPS53316 G008.png Figure 14. Efficiency vs Output Current, DE Mode
TPS53316 G010.png Figure 16. Efficiency vs Output Current, FCCM
TPS53316 G012.png Figure 18. Efficiency vs Output Current, HEF Mode
TPS53316 G014.png Figure 20. Efficiency vs Output Current, FCCM
TPS53316 G016.png Figure 22. Efficiency vs Output Current, FCCM
TPS53316 wave02_lusap5.gif Figure 24. Prebiased Start-up
TPS53316 wave04_lusap5.gif Figure 26. UVLO Start-Up Waveform
TPS53316 wave06_lusap5.gif Figure 28. Output Voltage Ripple – DE Mode
TPS53316 wave08_lusap5.gif Figure 30. Load Transient – DE Mode
TPS53316 wave13_lusap5.gif Figure 32. HEF Mode DCM and CCM Transition
TPS53316 wave10_lusap5.gif Figure 34. Short-Circuit Protection
TPS53316 G023.png
Figure 36. Safe Operating Area