bq27741-G1 Single-Cell Li-Ion Battery Fuel Gauge with Integrated Protection

8.3.5.2.1 Low Battery Capacity

This feature works identically to SOC1. It uses the same data flash entries as SOC1 and triggers interrupts as long as SOC1 = 1 and HDQIntEN = 1.

8.3.5.2.2 Temperature

This feature triggers an interrupt based on the OTC (Overtemperature in Charge) or OTD (Overtemperature in Discharge) condition being met. It uses the same data flash entries as OTC or OTD and triggers interrupts as long as either the OTD or OTC condition is met and HDQIntEN = 1. (See details in HDQ Host Interruption.)

8.3.5.3.1 I²C Time Out

The I²C engine releases both SDA and SCL lines if the I²C bus is held low for about 2 seconds. If the fuel gauge was holding the lines, releasing them frees the master to drive the lines.

8.3.5.3.2 I²C Command Waiting Time

To ensure the correct results of a command with the 400-kHz I²C operation, a proper waiting time must be added between issuing a command and reading the results. For subcommands, the following diagram shows the waiting time required between issuing the control command and reading the status with the exception of the checksum command. A 100-ms waiting time is required between the checksum command and reading the result. For read-write standard commands, a minimum of 2 seconds is required to get the result updated. For read-only standard commands, there is no waiting time required, but the host must not issue any standard command more than two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the watchdog timer.

Figure 9. I²C Command Waiting Time

The I²C clock stretch could happen in a typical application. A maximum 80-ms clock stretch could be observed during the flash updates. There is up to a 270-ms clock stretch after the OCV command is issued.

8.4.4.2.1 VIRTUAL SHUTDOWN Mode

In this mode, the fuel gauge is not functional and only certain portions of analog circuitry are running to allow device wakeup from shutdown and low voltage charging.

8.4.4.2.2 UNDERVOLTAGE FAULT Mode

In this mode, the voltage on VPWR pin is below V_UVP and the charger is connected. As soon as the charger disconnects, the fuel gauge transitions into ANALOG SHUTDOWN mode to save power.

The fuel gauge can enter this mode from LOW VOLTAGE CHARGING mode when the battery pack is being charged from a deeply discharged state or from NORMAL mode when the battery pack is being discharged below the allowed voltage.

When the battery pack is charged above V_UVPREL, the fuel gauge transitions to NORMAL mode.

8.4.4.2.3 NORMAL Mode

In this mode, the protector is fully powered and operational. Both CHG and DSG FETs are closed, while further operation is determined by the firmware. The protector is continuously checking for all faults.

The CHG or DSG FET may be commanded to be opened via the protector register by the firmware, but it does not affect protector operation or change the mode of operation.

Firmware can also command the fuel gauge to go into SHUTDOWN mode based on the command from the host. In this case, firmware sets the shutdown bit to indicate intent to go into SHUTDOWN mode. The fuel gauge then transitions to SHUTDOWN WAIT mode.

8.4.4.2.4 SHUTDOWN WAIT Mode

In this mode, the shutdown bit was set by the firmware and the fuel gauge initiated the shutdown sequence.

The shutdown sequence is as follows:

1. Open both CHG and DSG FETs.
2. Determine if any faults are set. If any faults are set, then go back to NORMAL mode.
3. Wait for charger removal. Once the charger is removed, turn off the LDO, which puts the fuel gauge into ANALOG SHUTDOWN mode.

8.4.4.2.5 OVERCURRENT IN DISCHARGE (OCD) and SHORT-CIRCUIT IN DISCHARGE (SCD) FAULT Mode

In this mode, a short-circuit in discharge (SCD) or overcurrent in discharge (OCD) protection fault is detected when the voltage across the sense resistor continuously exceeds the configured V_OCD or V_SCD thresholds for longer than the configured delay.

The fuel gauge enables the fault removal detection circuitry, which monitors load removal. A special high resistance load is switched on to monitor load presence. The OCD/SCD fault is cleared when the load is removed, which causes the fuel gauge to transition into NORMAL mode.

8.4.4.2.6 OVERCURRENT IN CHARGE (OCC) FAULT Mode

In this mode, an overcurrent in charge (OCC) protection fault is detected when the voltage across the sense resistor continuously exceeds the configured V_OCC for longer than the configured delay.

The fuel gauge enables the fault removal detection circuitry, which monitors the charger removal. The OCC fault is cleared once the charger voltage drops below the cell voltage by more than 300 mV, which causes the fuel gauge to transition to NORMAL mode.

8.4.4.2.7 OVERVOLTAGE PROTECTION (OVP) FAULT Mode

In this mode, an OVERVOLTAGE PROTECTION (OVP) fault mode is entered when the voltage on VPWR pin continuously exceeds the configured V_OVP threshold for longer than the configured delay.

The fuel gauge enables the fault removal detection circuitry, which monitors the charger removal. The OVP fault is cleared once the charger voltage drops below the cell voltage by more than 300 mV and the cell voltage drops below V_OVPREL, which causes the fuel gauge to transition to NORMAL mode.

Table 3. Key Data Flash Parameters for Configuration

9.2.1.2.1 BAT Voltage Sense Input

A ceramic capacitor at the input to the BAT pin is used to bypass AC voltage ripple to ground, greatly reducing its influence on battery voltage measurements. It is most effective in applications with load profiles that exhibit high frequency current pulses (that is, cell phones), but is recommended for use in all applications to reduce noise on this sensitive high impedance measurement node.

The series resistor between the battery and the BAT input is used to limit current that could be conducted through the chip-scale package's solder bumps in the event of an accidental short during the board assembly process. The resistor is not likely to survive a sustained short condition (depends on power rating); however, it damages the much cheaper resistor component over suffering damage to the fuel gauge die itself.

9.2.1.2.2 SRP and SRN Current Sense Inputs

The filter network at the input to the coulomb counter is intended to improve differential mode rejection of voltage measured across the sense resistor. These components should be placed as close as possible to the coulomb counter inputs and the routing of the differential traces length-matched in order to best minimize impedance mismatch-induced measurement errors. The single-ended ceramic capacitors should be tied to the battery voltage node (preferably to a large copper pour connected to the SRN side of the sense resistor) in order to further improve common-mode noise rejection. The series resistors between the CC inputs and the sense resistor should be at least 200 Ω in order to mitigate SCR-induced latch-up due to possible ESD events.

9.2.1.2.3 Sense Resistor Selection

Any variation encountered in the resistance present between the SRP and SRN pins of the fuel gauge will affect the resulting differential voltage and derived current it senses. As such, it is recommended to select a sense resistor with minimal tolerance and temperature coefficient of resistance (TCR) characteristics. The standard recommendation based on best compromise between performance and price is a 1% tolerance, 50-ppm drift sense resistor with a 1-W power rating.

9.2.1.2.4 TS Temperature Sense Input

Similar to the BAT pin, a ceramic decoupling capacitor for the TS pin is used to bypass AC voltage ripple away from the high-impedance ADC input, minimizing measurement error. Another helpful advantage is that the capacitor provides additional ESD protection since most thermistors are handled and manually soldered to the PCB as a separate step in the factory production flow. It should be placed as close as possible to the respective input pin for optimal filtering performance.

9.2.1.2.5 Thermistor Selection

The fuel gauge temperature sensing circuitry is designed to work with a negative temperature coefficient-type (NTC) thermistor with a characteristic 10-kΩ resistance at room temperature (25°C). The default curve-fitting coefficients configured in the fuel gauge specifically assume a 103AT-2 type thermistor profile and so that is the default recommendation for thermistor selection purposes. Moving to a separate thermistor resistance profile (for example, JT-2 or others) requires an update to the default thermistor coefficients in data flash to ensure highest accuracy temperature measurement performance.

9.2.1.2.6 VPWR Power Supply Input Filtering

A ceramic capacitor is placed at the input to the fuel gauge's internal LDO in order to increase power supply rejection (PSR) and improve effective line regulation. It ensures that voltage ripple is rejected to ground instead of coupling into the device's internal supply rails.

9.2.1.2.7 REG25 LDO Output Filtering

A ceramic capacitor is also needed at the output of the internal LDO to provide a current reservoir for fuel gauge load peaks during high peripheral utilization. It acts to stabilize the regulator output and reduce core voltage ripple inside of the device.

9.2.1.2.8 Communication Interface Lines

A protection network composed of resistors and zener diodes is recommended on each of the serial communication inputs to protect the fuel gauge from serious ESD transients. The Zener should be selected to break down at a voltage larger than the typical pullup voltage for these lines but less than the internal diode clamp breakdown voltage of the device inputs (approximately 6 V). A zener voltage of 5.6 V is typically recommended. The series resistors are used to limit the current into the Zener diode and prevent component destruction due to thermal strain once it goes into breakdown. 100 Ω is typically recommended for these resistance values.

9.2.1.2.9 PACKP Voltage Sense Input

Inclusion of a 2-kΩ series resistor on the PACKP input allows it to tolerate a charger overvoltage event up to 28 V without device damage. The resistor also protects the device in the event of a reverse polarity charger input, since the substrate diode will be forward biased and attempt to conduct charger current through the fuel gauge (as well as the high FETs). An external reverse charger input FET clamp can be added to short the DSG FET gate to its source terminal, forcing the conduction channel off when negative voltage is present at PACK+ input to the battery pack and preventing large battery discharge currents. A ceramic capacitor connected at the PACKP pin helps to filter voltage into the comparator sense lines used for checking charger and load presence. In addition, in the LOW VOLTAGE CHARGING state, the minimal circuit elements that are operational are powered from this input pin and require a stable supply.

9.2.1.2.10 CHG and DSG Charge Pump Voltage Outputs

The series resistors used at the DSG and CHG output pins serve to protect them from damaging ESD events or breakdown conditions, allowing the resistors to be damaged in place of the fuel gauge itself. An added bonus is that they also help to limit in-rush currents due to use of FETs with large gate capacitance, allowing a smooth ramp of power-path connection turn-on to the system.

9.2.1.2.11 N-Channel FET Selection

The selection of N-channel FETs for a single-cell battery pack design depends on a variety of factors including package type, size, and device cost as well as performance metrics such as drain-to-source resistance (rDS(on)), gate capacitance, maximum current and power handling, and similar. At a minimum, it is recommended that the selected FETs have a drain-to-source voltage (VDS) and gate-to-source (VGS) voltage tolerance of 12 V. Some FETs are designed to handle as much as 24 V between the drain and source terminals and this would provide an increased safety margin for the pack design. Additionally, the DC current rating should be high enough to safely handle sustained current in charge or discharge direction just below the maximum threshold tolerances of the configured OCC and OCD protections and the lowest possible sense resistance value based on tolerance and TCR considerations, or vice-versa. This ensures that there is sufficient power dissipation margin given a worst-case scenario for the fault detections. In addition, striving for minimal FET resistance at the expected gate bias as well as lowest gate capacitance will help reduce conduction losses and increase power efficiency as well as achieve faster turn-on and turn-off times for the FETs. Many of these FETs are now offered as dual, back-to-back N-channel FETs in wafer-chip scale (WCSP) packaging, decreasing both BOM count and shrinking necessary board real estate to accommodate the components. Finally, refer to the safe operating area (SOA) curves of the target FETs to ensure that the boundaries are never violated based on all possible load conditions in the end application. The CSD83325L is an excellent example of a FET solution that meets all of the aforementioned criteria, offering rDS(on) of 10.3 mΩ and VDS of 12 V with back-to-back N-channel FETs in a chip-scale package, a perfect fit for battery pack designs.

9.2.1.2.12 Additional ESD Protection Components

The additional capacitors placed across the CHG and DSF FET source pins as well as between PACK+ and ground help to bolster and greatly improve the ESD robustness of the pack design. The former components shunt damaging transients around the FETs and the latter components attempt to bypass such pulses to PACK– before they couple further into the battery pack PCB. Two series capacitors are used for each of these protection areas to prevent a battery short in the event of a single capacitor failure.