Table 2. I_WAKE Threshold Settings⁽¹⁾

8.3.4.1 Charge and Discharge Counting

The integrating delta-sigma ADC gauges the charge or discharge flow of the battery by measuring the voltage drop across a small-value sense resistor between the SRP and SRN pins. The integrating ADC measures bipolar signals and detects charge activity when V_SR = V_SRP – V_SRN is positive and discharge activity when V_SR = V_SRP – V_SRN is negative. The fuel gauge continuously integrates the signal over time using an internal counter.

8.3.4.2 Voltage

The fuel gauge updates cell voltages at 1-second intervals when in NORMAL mode. The internal ADC of the fuel gauge measures the voltage, and scales and calibrates it appropriately. Voltage measurement is automatically compensated based on temperature. This data is also used to calculate the impedance of the cell for Impedance Track fuel gauging.

8.3.4.3 Current

The fuel gauge uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current using a 5-mΩ to 20-mΩ typical sense resistor.

8.3.4.4 Auto-Calibration

The bq27741-G1 device provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for maximum charge measurement accuracy, and performs auto-calibration before entering the SLEEP mode.

8.3.4.5 Temperature

The fuel gauge external temperature sensing is optimized with the use of a high-accuracy negative temperature coefficient (NTC) thermistor with R25 = 10 kΩ ± 1% and B25/85 = 3435 kΩ ± 1% (such as Semitec 103AT for measurement). The fuel gauge can also be configured to use its internal temperature sensor. The fuel gauge uses temperature to monitor the battery-pack environment, which is used for fuel gauging and cell protection functionality.

8.3.5.1 HDQ Single-Pin Serial Interface

The HDQ interface is an asynchronous return-to-one protocol where a processor sends the command code to the fuel gauge. With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted first. The DATA signal on pin 12 is open-drain and requires an external pullup resistor. The 8-bit command code consists of two fields: the 7-bit HDQ command code (bits 0 through 6) and the 1-bit RW field (MSB bit 7). The RW field directs the fuel gauge to either one of the following:

• Store the next 8 bits of data to a specified register, or
• Output 8 bits of data from the specified register.

The HDQ peripheral can transmit and receive data as either an HDQ master or slave.

HDQ serial communication is normally initiated by the host processor sending a break command to the fuel gauge. A break is detected when the DATA pin is driven to a logic low state for a time t_(B) or greater. The DATA pin then is returned to its normal ready logic high state for a time t_(BR). The fuel gauge is now ready to receive information from the host processor.

The fuel gauge is shipped in the I²C mode. TI provides tools to enable the HDQ peripheral.

8.3.5.2 HDQ Host Interruption

The default fuel gauge behaves as an HDQ slave-only device. If the HDQ interrupt function is enabled, the fuel gauge is capable of mastering and also communicating to a HDQ device. There is no mechanism for negotiating which is to function as the HDQ master, and care must be taken to avoid message collisions. The interrupt is signaled to the host processor with the fuel gauge mastering an HDQ message. This message is a fixed message that signals the interrupt condition. The message itself is 0x80 (slave write to register 0x00) with no data byte being sent as the command is not intended to convey any status of the interrupt condition. The HDQ interrupt function is not public and is only enabled by command.

When the SET_HDQINTEN subcommand is received, the fuel gauge detects any of the interrupt conditions and asserts the interrupt at 1-s intervals until either:

• The CLEAR_HDQINTEN subcommand is received, or
• The number of tries for interrupting the host has exceeded a predetermined limit. After the interrupt event, interrupts are automatically disabled. To re-enable interrupts, SET_HDQINTEN needs to be sent.

8.3.5.3 I²C Interface

The fuel gauge supports the standard I²C read, incremental read, one-byte write quick read, and functions. The 7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit device address is therefore 0xAA or 0xAB for write or read, respectively.

Figure 8. Supported I²C Formats

1. 1-byte write
2. Quick read
3. 1-byte read
4. Incremental read (S = Start, Sr = Repeated Start, A = Acknowledge, N = No Acknowledge, and P = Stop).

The quick read returns data at the address indicated by the address pointer. The address pointer, a register internal to the I²C communication engine, increments whenever data is acknowledged by the fuel gauge or the I²C master. Quick writes function in the same manner and are a convenient means of sending multiple bytes to consecutive command locations (such as two-byte commands that require two bytes of data).

Attempt to write a read-only address (NACK after data sent by master):

Attempt to read an address above 0x7F (NACK command):

Attempt at incremental writes (NACK all extra data bytes sent):

Incremental read at the maximum allowed read address:

The I²C engine releases both SDA and SCL if the I²C bus is held low for t_(BUSERR). If the fuel gauge was holding the lines, releasing them frees the master to drive the lines. If an external condition is holding either of the lines low, the I²C engine enters the low-power SLEEP mode.

8.3.5.3.2 I²C Command Waiting Time

To ensure the correct results of a command with the 400-kHz I²C operation, a proper waiting time must be added between issuing a command and reading the results. For subcommands, the following diagram shows the waiting time required between issuing the control command and reading the status with the exception of the checksum command. A 100-ms waiting time is required between the checksum command and reading the result. For read-write standard commands, a minimum of 2 seconds is required to get the result updated. For read-only standard commands, there is no waiting time required, but the host must not issue any standard command more than two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the watchdog timer.

Figure 9. I²C Command Waiting Time

The I²C clock stretch could happen in a typical application. A maximum 80-ms clock stretch could be observed during the flash updates. There is up to a 270-ms clock stretch after the OCV command is issued.

8.4.4.1 High-Side N-Channel FET Charge and Discharge FET Drive

The CHG or DSG FET is turned on by pulling the FET gate input up to V_FETON. The FETs are turned off by pulling the FET gate input down to V_SS. These FETs are automatically turned off by the protector based on the detected protection faults, or when commanded to turn off via the FETTest(0x74/0x75) extended command. Once the protection fault(s) is cleared, the FETs may be turned on again.

8.4.4.2 Operating Modes

The battery protector has several operating modes:

• Virtual SHUTDOWN mode
  • ANALOG SHUTDOWN
  • Low voltage charging
• UVP fault (POR state)
• NORMAL mode
• SHUTDOWN WAIT
• OCD or SCD FAULT mode
• OCC FAULT mode
• OVP FAULT mode

The relationships among these modes are shown in Figure 10.

Figure 10. Operating Modes

8.4.4.3 Firmware Control of Protector

The firmware has control to open the CHG FET or DSG FET independently by overriding hardware control. However, it has no control to close the CHG FET or DSG FET and can only disable the FET override.