SLUUA65E april 2014 – june 2023 BQ28Z610
Class | Subclass | Name | Type | Min | Max | Default | Description |
---|---|---|---|---|---|---|---|
Settings | Configuration | FET Options | H1 | 0x00 | 0xFF | 0x20 | Bit 0: Reserved Bit 1: Reserved Bit 2: OTFET—FET action in OVERTEMPERATURE mode 0 = No FET action for overtemperature condition (default) 1 = CHG and DSG FETs will be turned off for overtemperature conditions. Bit 3: CHGSU—FET action in CHARGE SUSPEND mode 0 = FET active (default) 1 = Charging or precharging disabled, FET off Bit 4: CHGIN—FET action in CHARGE INHIBIT mode 0 = FET active (default) 1 = Charging or precharging disabled, FET off Bit 5: CHGFET—FET action on valid charge termination 0 = FET active (default) 1 = Charging or precharging disabled, FET off Bit 6: SLEEPCHG—CHG FET enabled during sleep 0 = CHG FET off during sleep (default) 1 = CHG FET remains on during sleep. Bit 7: Reserved |
Settings | Configuration | I2C Gauging Configuration | H1 | 0x00 | 0x0F | 0x04 | Bit 0:
RSOCL—RelativeStateOfCharge() and
RemainingCapacity() behavior at end of charge 0 = Actual value shown (default) 1 = Held at 99% until valid charge termination. On entering valid charge termination, updates to 100%. Bit 1: RSOC_HOLD—Prevents RSOC from increasing during discharge 0 = RSOC not limited 1 = RSOC not allowed to increase during discharge Bit 2: LOCK0—Keeps RemainingCapacity() and RelativeStateOfCharge() from jumping back during relaxation after 0 was reached during discharge. 0 = Disabled (default) 1 = Enabled Bit 7:3: Reserved |
Settings | Configuration | I2C Configuration | H1 | 0x00 | 0xFF | 0x01 | Bit 0: BCAST—Enables the charging
broadcast from device to smart charger 0 = Disabled 1 = Enabled (default) Bit 1: Reserved Bit 2: Reserved Bit 3: XL—Enables 400-kHz COM mode 0 = Normal bus speed (default) 1 = 400-kHz bus speed (slave mode) Bit 5:4: Reserved Bit 6: TO_STRETCH_EN—Enables bus timeouts (15-ms clock high and 25ms clock low) 0 = Disabled (default) 1 = Enabled Bit 7: FLASH_BUSY_WAIT—Enables clock stretching during a flash program or erase operation 0 = Disabled (default) 1 = Enabled |
Settings | Configuration | Power Config | H1 | 0x00 | 0x01 | 0x00 | Bit 0: AUTO_SHIP_EN—Automatically shut
down for shipment 0 = Disables the auto shutdown feature (default) 1 = Enables auto shutdown after the device is in SLEEP mode without communication for a set period of time. Bit 3: 1: Reserved Bit 4: SLP_ACCUM—Enables sleep charge accumulation 1 = Enables sleep charge accumulation 0 = Disables sleep charge accumulation (default) Bit 5: SLEEPWKCHG—Enables sleep wake charge feature 1 = Enables the sleep wake charge feature 0 = Disables sleep wake charge feature (default) Bit 7: 6: Reserved |
Settings | Configuration | I/O Config | H1 | 0x00 | 0x03 | 0x00 | Bit 0: BTP_EN—Enables assertion of BTP
terminal 0 = Disables assertion of the BTP terminal when BTP is triggered (default). 1 = Enables assertion of BTP terminal when BTP is triggered Bit 1: BTP_POL—Control polarity of BTP terminal 0 = BTP terminal is asserted low when BTP is triggered (default). 1 = BTP terminal is asserted high when BTP is triggered. Bit 7:2: Reserved |
Settings | Configuration | SOC Flag Config A | H2 | 0x0000 | 0xFFFF | 0x0C8C | Bit 0: TDSETV—Enables the TD flag set
by the cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 1: TDCLEARV—Enables the TD flag clear by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 2: TDSETRSOC—Enables the TD flag set by RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 3: TDCLEARRSOC—Enables the TD flag cleared by the RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 4: TCSETV—Enables the TC flag set by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 5: TCCLEARV—Enables the TC flag clear by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 6: TCSETRSOC—Enables the TC flag set by the RSOC threshold 0 = Disabled (default) 1 = Enabled Bit 7: TCCLEARRSOC—Enables the TC flag cleared by the RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 8: Reserved Bit 9: Reserved Bit 10: FCSETVCT—Enables the FC flag set by primary charge termination 0 = Disabled 1 = Enabled (default) Bit 11: TCSETVCT—Enables the TC flag set by primary charge termination 0 = Disabled 1 = Enabled (default) Bit 15: 12: Reserved |
Settings | Configuration | SOC Flag Config B | H1 | 0x0000 | 0x00FF | 0x008C | Bit 0: FDSETV—Enables the FD flag set
by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 1: FDCLEARV—Enables the FD flag clear by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 2: FDSETRSOC—Enables the FD flag set by RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 3: FDCLEARRSOC—Enables the FD flag clear by RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 4: FCSETV—Enables the FC flag set by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 5: FCCLEARV—Enables the FC flag clear by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 6: FCSETRSOC—Enables the FC flag set by RSOC threshold 0 = Disabled (default) 1 = Enabled Bit 7: FCCLEARRSOC—Enables the FC flag clear by RSOC threshold 0 = Disabled 1 = Enabled (default) |
Settings | Configuration | Charging Configuration | H1 | 0x00 | 0x3F | 0x00 | Bit 0: CRATE—ChargeCurrent rate 0 = No adjustment to ChargingCurrent() (default) 1 = ChargingCurrent() adjusted based on FullChargeCapacity()/DesignCapacity() Bit 7:1: Reserved |
Settings | Configuration | Temperature Enable | H1 | 0x00 | 0x03 | 0x03 | Bit 0: internal TS— Enables internal
TS 0 = Disables internal TS (default) 1 = Enables internal TS Bit 1: TS1—Enables TS1 0 = Disables TS1 1 = Enables TS1 (default) Bit 7:2: Reserved |
Settings | Configuration | DA Configuration | H1 | 0x00 | 0xFF | 0x11 | Bit 0: CC0—Cell Count 0 = 1 cell 1 = 2 cell Bit 1: Reserved Bit 2: Reserved Bit 3: IN_SYSTEM_SLEEP—In-system SLEEP mode 0 = Disables (default) 1 = Enables Bit 4: SLEEP—SLEEP Mode 0 = Disables SLEEP mode 1 = Enables SLEEP mode (default) Bit 5: Reserved Bit 6: CTEMP—Cell Temperature protection source 0 = MAX (default) 1 = Average Bit 7: Reserved |
Settings | Configuration | IT Gauging Configuration | H2 | 0x0000 | 0xFFFF | 0xD4DE | Bit 0: CCT—Cycle count threshold 0 = Use CC % of DesignCapacity() (default) 1 = Use CC % of FullChargeCapacity() Bit 1: CSYNC—Sync RemainingCapacity() with FullChargeCapacity() at valid charge termination 0 = Not synchronized 1 = Synchronized (default) Bit 2: RFACTSTEP—Allow Ra update to limit before disqualifying further updates 0 = If (new Ra)/(old Ra) > 3, Ra update is not completed, and Ra updates are disabled. 1 = If (new Ra)/(old Ra) > 3, one Ra update is completed limited to factor of 3, and further Ra updates are disabled. Bit 3: OCVFR—Open Circuit Voltage Flat Region 0 = Disabled 1 = Enabled (default) Bit 4: Reserved Bit 5: Reserved Bit 6: RSOC_CONV—See Section 6.6. Bit 7: FAST_QMax_LRN—See Section 6.6. Bit 8: FAST_Qmax_FLD—See Section 6.6. Bit 9: CELL_TERM—See Section 6.6. Bit 10: FF_NEAR_EDV—See Section 6.6. Bit 11: RELAX_JUMP_OK—See Section 6.6. Bit 12: SMOOTH—See Section 6.6. Bit 13: Reserved Bit 14: Reserved Bit 15: Reserved |
Settings | Configuration | Balancing Configuration | H1 | 0x00 | 0xFF | 0x01 | Bit 0: CB—Cell balancing 0 = Cell balancing disabled 1 = Cell balancing enabled (default) Bit 1: Reserved Bit 2: CBR—Cell balancing at rest 0 = Cell balancing at rest is disabled (default). 1 = Cell balancing at rest is enabled. Bit 7:3: Reserved |