SLUUAQ3A April 2016 – October 2022 BQ4050
This command returns the PFAlert() flags on ManufacturerBlockAccess() or ManufacturerData().
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TS4 | TS3 | TS2 | TS1 | RSVD | RSVD | OPNC | RSVD | RSVD | 2LVL | AFEC | AFER | FUSE | RSVD | DFE TF | CFE TF |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | RSVD | RSVD | VIMA | VIMR | RSVD | RSVD | RSVD | RSVD | SOTF | RSVD | SOT | SOCD | SOCC | SOV | SUV |
TS4 (Bit 31): Open Thermistor–TS4 Failure | ||
1 = | Detected | |
0 = | Not Detected | |
TS3 (Bit 30): Open Thermistor–TS3 Failure | ||
1 = | Detected | |
0 = | Not Detected | |
TS2 (Bit 29): Open Thermistor–TS2 Failure | ||
1 = | Detected | |
0 = | Not Detected | |
TS1 (Bit 28): Open Thermistor–TS1 Failure | ||
1 = | Detected | |
0 = | Not Detected | |
RSVD (Bits 27–26): Reserved. Do not use. | ||
OPNC (Bit 25): Open Cell Tab Connection Failure | ||
1 = | Detected | |
0 = | Not Detected | |
RSVD (Bits 24–23): Reserved. Do not use. | ||
2LVL (Bit 22): Second Level Protector Failure | ||
1 = | Detected | |
0 = | Not Detected | |
AFEC (Bit 21): AFE Communication Failure | ||
1 = | Detected | |
0 = | Not Detected | |
AFER (Bit 20): AFE Register Failure | ||
1 = | Detected | |
0 = | Not Detected | |
FUSE (Bit 19): Chemical Fuse Failure | ||
1 = | Detected | |
0 = | Not Detected | |
DFETF (Bit 17): Discharge FET Failure | ||
1 = | Detected | |
0 = | Not Detected | |
CFETF (Bit 16): Charge FET Failure | ||
1 = | Detected | |
0 = | Not Detected | |
RSVD (Bits 15–13): Reserved. Do not use. | ||
VIMA (Bit 12): Voltage Imbalance While Pack Is Active Failure | ||
1 = | Detected | |
0 = | Not Detected | |
VIMR (Bit 11): Voltage Imbalance While Pack Is At Rest Failure | ||
1 = | Detected | |
0 = | Not Detected | |
RSVD (Bits 10–7): Reserved. Do not use. | ||
SOTF (Bit 6): Safety Overtemperature FET Failure | ||
1 = | Detected | |
0 = | Not Detected | |
RSVD (Bit 5): Reserved. Do not use. | ||
SOT (Bit 4): Safety Overtemperature Cell Failure | ||
1 = | Detected | |
0 = | Not Detected | |
SOCD (Bit 3): Safety Overcurrent in Discharge | ||
1 = | Detected | |
0 = | Not Detected | |
SOCC (Bit 2): Safety Overcurrent in Charge | ||
1 = | Detected | |
0 = | Not Detected | |
SOV (Bit 1): Safety Cell Overvoltage Failure | ||
1 = | Detected | |
0 = | Not Detected | |
SUV (Bit 0): Safety Cell Undervoltage Failure | ||
1 = | Detected | |
0 = | Not Detected |