SLUUBW5A July   2018  – September 2021 BQ34Z100-G1

 

  1. 1 Read This First
    1. 1.1 About This Manual
    2. 1.1 Notational Conventions
    3. 1.1 Glossary
    4. 1.1 Trademarks
  2. 1 Introduction
  3. 2 Data Commands
    1. 2.1 Standard Data Commands
      1. 2.1.1  Control(): 0x00/0x01
        1. 2.1.1.1  CONTROL_STATUS: 0x0000
        2. 2.1.1.2  DEVICE TYPE: 0x0001
        3. 2.1.1.3  FW_VERSION: 0x0002
        4. 2.1.1.4  HW_VERSION: 0x0003
        5. 2.1.1.5  RESET_DATA: 0x0005
        6. 2.1.1.6  PREV_MACWRITE: 0x0007
        7. 2.1.1.7  CHEM ID: 0x0008
        8. 2.1.1.8  BOARD_OFFSET: 0x0009
        9. 2.1.1.9  CC_OFFSET: 0x000A
        10. 2.1.1.10 CC_OFFSET_SAVE: 0x000B
        11. 2.1.1.11 DF_VERSION: 0x000C
        12. 2.1.1.12 SET_FULLSLEEP: 0x0010
        13. 2.1.1.13 STATIC_CHEM_DF_CHKSUM: 0x0017
        14. 2.1.1.14 SEALED: 0x0020
        15. 2.1.1.15 IT ENABLE: 0x0021
        16. 2.1.1.16 CAL_ENABLE: 0x002D
        17. 2.1.1.17 RESET: 0x0041
        18. 2.1.1.18 EXIT_CAL: 0x0080
        19. 2.1.1.19 ENTER_CAL: 0x0081
        20. 2.1.1.20 OFFSET_CAL: 0x0082
      2. 2.1.2  StateOfCharge(): 0x02
      3. 2.1.3  MaxError(): 0x03
      4. 2.1.4  RemainingCapacity(): 0x04/0x05
      5. 2.1.5  FullChargeCapacity(): 0x06/07
      6. 2.1.6  Voltage(): 0x08/0x09
      7. 2.1.7  AverageCurrent(): 0x0A/0x0B
      8. 2.1.8  Temperature(): 0x0C/0x0D
      9. 2.1.9  Flags(): 0x0E/0x0F
      10. 2.1.10 FlagsB(): 0x12/0x13
      11. 2.1.11 Current(): 0x10/0x11
    2. 2.2 Extended Data Commands
      1. 2.2.1  AverageTimeToEmpty(): 0x18/0x19
      2. 2.2.2  AverageTimeToFull(): 0x1A/0x1B
      3. 2.2.3  PassedCharge(): 0x1C/0x1D
      4. 2.2.4  DOD0Time(): 0x1E/0x1F
      5. 2.2.5  AvailableEnergy(): 0x24/0x25
      6. 2.2.6  AveragePower(): 0x26/0x27
      7. 2.2.7  SerialNumber(): 0x28/0x29
      8. 2.2.8  InternalTemperature(): 0x2A/0x2B
      9. 2.2.9  CycleCount(): 0x2C/0x2D
      10. 2.2.10 StateOfHealth(): 0x2E/0x2F
      11. 2.2.11 ChargeVoltage(): 0x30/0x31
      12. 2.2.12 ChargeCurrent(): 0x32/0x33
      13. 2.2.13 PackConfiguration(): 0x3A/0x3B
      14. 2.2.14 DesignCapacity(): 0x3C/0x3D
      15. 2.2.15 DataFlashClass(): 0x3E
      16. 2.2.16 DataFlashBlock(): 0x3F
      17. 2.2.17 AuthenticateData/BlockData(): 0x40…0x53
      18. 2.2.18 AuthenticateChecksum/BlockData(): 0x54
      19. 2.2.19 BlockData(): 0x55…0x5F
      20. 2.2.20 BlockDataChecksum(): 0x60
      21. 2.2.21 BlockDataControl(): 0x61
      22. 2.2.22 GridNumber(): 0x62
      23. 2.2.23 LearnedStatus(): 0x63
      24. 2.2.24 Dod@Eoc(): 0x64/0x65
      25. 2.2.25 QStart(): 0x66/0x67
      26. 2.2.26 TrueRC(): 0x68/0x69
      27. 2.2.27 TrueFCC(): 0x6A/0x6B
      28. 2.2.28 StateTime(): 0x6C/0x6D
      29. 2.2.29 QmaxPassedQ(): 0x6E/0x6F
      30. 2.2.30 DOD0(): 0x70/0x71
      31. 2.2.31 QmaxDod0(): 0x72/0x73
      32. 2.2.32 QmaxTime(): 0x74/0x75
      33. 2.2.33 Data Flash Interface
        1. 2.2.33.1 Accessing Data Flash
        2. 2.2.33.2 Manufacturer Information Block
        3. 2.2.33.3 Access Modes
        4. 2.2.33.4 Sealing/Unsealing Data Flash Access
  4. 3 Fuel Gauging
    1. 3.1  Overview
    2. 3.2  Impedance Track Variables
      1. 3.2.1  Load Mode
      2. 3.2.2  Load Select
      3. 3.2.3  Reserve Cap-mAh
      4. 3.2.4  Reserve Cap-mWh/cWh
      5. 3.2.5  Design Energy Scale
      6. 3.2.6  Dsg Current Threshold
      7. 3.2.7  Chg Current Threshold
      8. 3.2.8  Quit Current, Dsg Relax Time, Chg Relax Time, and Quit Relax Time
      9. 3.2.9  Qmax
      10. 3.2.10 Update Status
      11. 3.2.11 Avg I Last Run
      12. 3.2.12 Avg P Last Run
      13. 3.2.13 Cell Delta Voltage
      14. 3.2.14 Ra Tables
      15. 3.2.15 StateOfCharge() Smoothing
      16. 3.2.16 Charge Efficiency
      17. 3.2.17 Lifetime Data Logging
    3. 3.3  Device Configuration
      1. 3.3.1 Pack Configuration Register
      2. 3.3.2 Pack Configuration B Register
      3. 3.3.3 Pack Configuration C Register
    4. 3.4  Voltage Measurement and Calibration
      1. 3.4.1 1S Example
      2. 3.4.2 7S Example
      3. 3.4.3 Autocalibration
    5. 3.5  Temperature Measurement
    6. 3.6  Overtemperature Indication
      1. 3.6.1 Overtemperature: Charge
      2. 3.6.2 Overtemperature: Discharge
    7. 3.7  Charging and Charge Termination Indication
    8. 3.8  SCALED Mode
    9. 3.9  LED Display
    10. 3.10 Alert Signal
  5. 4 Communications
    1. 4.1 Authentication
    2. 4.2 Key Programming
    3. 4.3 Executing an Authentication Query
    4. 4.4 HDQ Single-Pin Serial Interface
    5. 4.5 I2C Interface
    6. 4.6 Switching Between I2C and HDQ Modes
      1. 4.6.1 Converting to HDQ Mode
      2. 4.6.2 Converting to I2C Mode
  6. 5 Device Functional Modes
    1. 5.1 NORMAL Mode
    2. 5.2 SLEEP Mode
    3. 5.3 FULL SLEEP Mode
  7. 6 Power Control
    1. 6.1 Reset Functions
    2. 6.2 Wake-Up Comparator
    3. 6.3 Flash Updates
  8. 7 Data Flash Summary
  9. 8 Gas Gauge Timing Considerations
    1. 8.1 Gauging Effects on I2C Transactions
    2. 8.2 HDQ Bus Effects on Gauging
    3. 8.3 Gauging Effects on HDQ Transactions
    4. 8.4 Manufacturer Timing Notes
  10. 9 HDQ Communication Basics
    1. 9.1 Basic HDQ Protocol
    2. 9.2 Break
    3. 9.3 Basic Timing
    4. 9.4 Reading 16-Bit Words
    5. 9.5 Host Processor Interrupts Using Discrete I/O Port for HDQ
    6. 9.6 Using UART Interface to HDQ
  11. 10Procedures to Seal and Unseal the Gauge
    1. 10.1 Unseal the Gauge to UNSEALED Mode
    2. 10.2 Unseal the Gauge to FULL ACCESS Mode
    3. 10.3 Seal the Gauge
  12. 11Impedance Track Gauge Configuration
    1. 11.1 Introduction
    2. 11.2 Determining ChemID
    3. 11.3 Learning Cycle
    4. 11.4 Common Problems Seen During the Learning Cycle
    5. 11.5 Test Gauge and Optimize
    6. 11.6 Finalize Golden File
    7. 11.7 Program and Test the PCB
  13. 12Revision History

9.5 Host Processor Interrupts Using Discrete I/O Port for HDQ

If the host implements the HDQ communication using a discrete processor I/O port, the timing of the transmitted HDQ data and the sampling of the received HDQ data depends on the host processor timing of the transitions on the HDQ line. If the HDQ communication routine is interrupted during a communication, it may cause the transmitted times to stretch, and the received data may not be interpreted correctly.

One solution is to disable interrupts during HDQ communication critical times. When the host is sending the address or data, there is no restriction on the time between each bit, so host interrupts can be enabled during the high time between bits. Interrupts may need to be disabled during the low bit times to ensure that the bit low times meet the required HDQ timing constraints. After the last address bit (a R/W bit) is sent on a read, interrupts also must be disabled to ensure that the received data is sampled correctly. Interrupts must be disabled during the entire receipt of the 8 data bit times.

If disabling interrupts during HDQ communication critical times is not feasible, another approach is to leave interrupts enabled, but to have all enabled interrupts set a flag that can be read to determine whether an interrupt occurred during an HDQ communication. The strategy would be to stop the communication with a break and then retry the communication if an interrupt occurred during an HDQ communication. This method requires that there be a reasonable probability of completing an HDQ communication without an interrupt.