SLUUBW5A July 2018 – September 2021 BQ34Z100-G1
The sources for gauge operations to impact I2C transactions are interrupt latency, command decode, and the execution of critical code sections. These result in variability to the clock stretches observed on the I2C bus. There is a slight variability in interrupt latency because the timing of communications is asynchronous to gauge processes. The execution path between a halted gauge and one with an active process can be slightly different. Command decoding adds several µs of variability to clock stretches; that is, some commands are decoded more quickly than others. The impact of critical sections is to impact clock stretching on the I2C bus. The most critical sections only add 5 µs to 10 µs of clock stretch. However, if the gauge has initiated an update to its flash data memory, it is possible to see a series of 2-ms to 20-ms clock stretches. With no synchronizing mechanism between the host and gauge, these stretches will appear as random occurrences to the host system.