SLUUCC7A September   2020  – April 2021 TPS562211

 

  1. 1Introduction
  2. 2Performance Specification Summary
  3. 3Modifications
    1. 3.1 MODE Pin Configuration
    2. 3.2 Output Voltage Setpoint
  4. 4Test Setup
    1. 4.1 Input/Output Connections
    2. 4.2 Start-Up Procedure
  5. 5Board Layout
    1. 5.1 Layout
    2. 5.2 EVM Picture
  6. 6Schematic, List of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 List of Materials
  7. 7Reference
  8. 8Revision History

4.1 Input/Output Connections

The TPS562211EVM is provided with input/output connectors and test points as shown in Table 4-1. Figure 4-1 shows connectors and jumpers placement on TPS562211EVM board.

A power supply capable of supplying 2 A must be connected to J1 through a pair of 20-AWG wires. The load must be connected to J2 through a pair of 20-AWG wires. The maximum load current capability is 2 A. Wire lengths must be minimized to reduce losses in the wires. Test point TP1 provides a place to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP3 is used to monitor the output voltage with TP4 as the ground reference.

GUID-20200923-CA0I-WBSP-FTF1-34FMCGXKL4BD-low.gifFigure 4-1 Connectors and Jumpers Placement
Table 4-1 Connection and Test Points
REFERENCE DESIGNATORFUNCTION
J1VIN (see Table 1-1 for VIN range)
J2VOUT, 3.3 V at 2 A maximum
J3EN control. Shunt EN to GND to disable.
J4Source selection for PGOOD
TP1VIN positive power point
TP3VOUT positive monitor point
TP2, TP4, TP7GND monitor point
TP5Test point for PG/SS measurment
TP6Switch node test point