SLUUCH1 June   2021 TPS62933

 

  1. 1TPS62933EVM-129 3-A, Regulator Evaluation Module
    1.     Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Modifications
    1. 3.1 Output Voltage Setpoint
  5. 4Test Setup and Results
    1. 4.1 Input/Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Load Transient Response
    4. 4.4 Output Voltage Ripple
    5. 4.5 Start-Up
    6. 4.6 Shut-Down
  6. 5Board Layout
    1. 5.1 Layout
  7. 6Schematic, List of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 List of Materials

Layout

The board layout for the TPS62933EVM is shown in Figure 5-1, Figure 5-2, and Figure 5-3. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS62933 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C6, C7, C8, and C9 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the switching node copper fill, signal ground copper fill and the feed back trace from the point of regulation to the top of the resistor divider network. Both the top layer and bottom layer use 2 oz copper thickness.

Figure 5-4 and Figure 5-5 are the TPS62933EVM board top view and bottom view, respectively.

Figure 5-1 TPS62933EVM Top Assembly
Figure 5-2 TPS62933EVM Top Layer
Figure 5-3 TPS62933EVM Bottom Layer
GUID-20210530-CA0I-37ND-QB8P-HQWPDDLCD4C5-low.jpg Figure 5-4 TPS62933EVM Board Top View
GUID-20210530-CA0I-1DCD-MCLV-K6DG0MHKH06R-low.jpg Figure 5-5 TPS62933EVM Board Bottom View