SLUUCH6B september   2022  – september 2023 TPS543B22

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Background
    2. 1.2 Before You Begin
    3. 1.3 Performance Characteristics Summary
  5. 2Configurations and Modifications
    1. 2.1 Output Voltage
    2. 2.2 Switching Frequency (FSEL Pin)
    3. 2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
    4. 2.4 Adjustable UVLO
  6. 3Test Setup and Results
    1. 3.1  Input/Output Connections
    2. 3.2  Efficiency
    3. 3.3  Output Voltage Regulation
    4. 3.4  Load Transient and Loop Response
    5. 3.5  Output Voltage Ripple
    6. 3.6  Input Voltage Ripple
    7. 3.7  Synchronizing to a Clock
    8. 3.8  Start-up and Shutdown with EN
    9. 3.9  Start-up and Shutdown with VIN
    10. 3.10 Start-up Into Pre-Bias
    11. 3.11 Hiccup Current Limit
    12. 3.12 Thermal Performance
  7. 4Board Layout
    1. 4.1 Layout
  8. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
  9. 6Revision History

3.2 Efficiency

Figure 3-1 and Figure 3-2 show the efficiency for both designs on the TPS543B22EVM. The test points listed in Table 3-3 are used for the efficiency measurement. Use these test points to minimize the contribution of PCB parasitic power loss to the measured power loss.

Some additional test setup considerations to minimize external sources of power dissipation are listed below.

  • Disable the other regulator to avoid including the switching quiescent current of the other regulator in the efficiency measurement.
  • Do not measure the SW pin of P2 with TP24 while measuring the efficiency of P2. Measuring the SW pin with this test point loads this node with 500 Ω and the efficiency measurement includes the power lost in this external resistance.
  • Remove the shunt from J8 to use default start voltage for P2.

Table 3-3 Efficiency Measurement Test Points
RELATED ICTEST POINT NAMEREFERENCE DESIGNATORFUNCTION
U1VIN_P1TP30Input voltage test point connected near pins of P1
VOUT_P1TP31Output voltage test point near output inductor of P1
PGND_EFF_P1TP36, TP33PGND reference test point for both input and output voltages Kelvin connected near P1
U2VIN_P2TP2Input voltage test point connected near pins of P2
VOUT_P2TP1Output voltage test point near output inductor of P2
PGND_EFF_P2TP9,TP16PGND reference test point for both input and output voltages Kelvin connected near P2
GUID-20230726-SS0I-BV1G-TM3P-QZQX3KTZMZGQ-low.svg
VOUT = 1.2V fSW = 2200 kHz
Figure 3-1 P1 Efficiency
GUID-20230405-SS0I-N5JD-KPWS-P88JN4CKPVL1-low.svg
VOUT = 1 V fSW = 1000 kHz
Figure 3-2 P2 Efficiency – Default Configuration