The switching node rise and fall times
must be minimized for minimum switching loss. Proper layout of the components to
minimize high frequency current path loop is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Follow this specific
order carefully to achieve the proper layout.
- Place input capacitor as close as possible to PMID pin and GND
pin connections and use shortest copper trace connection or GND plane.
- Place inductor input pin to SW
pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry
the charging current. Do not use multiple layers in parallel for this
connection. Minimize parasitic capacitance from this area to any other trace or
plane.
- Put output capacitor near to the inductor and the device. Ground
connections need to be tied to the IC ground with a short copper trace
connection or GND plane.
- Place decoupling capacitors next to the IC pins and make trace
connection as short as possible.
- Make sure that the number and
sizes of vias allow enough copper for a given current path.
See the EVM design for the recommended
component placement with trace and via locations.