The I²C serial communications interface in the BQ77307 device acts as a target device and supports rates up to 400 kHz with an optional CRC check. The BQ77307 initially powers up by default with CRC disabled, which is determined by the OTP settings factory programmed by TI. The host can change the CRC mode setting while in CONFIG_UPDATE mode, then the new setting takes effect upon exit of CONFIG_UPDATE mode.

The I²C device address (as an 8-bit value including target address and R/W bit) is set by default as 0x10 (write), 0x11 (read), which can be changed by the Settings:Configuration:I2C Address configuration setting.

The communications interface includes programmable timeout capability, with the internal I²C bus logic reset when an enabled timeout occurs:

• SCL Short Low Timeout - triggers if SCL stays low for approximately 25 ms. Enabled when Settings:Configuration:I2C Config[I2CCSLTO] is set.
• SCL Long Low Timeout - triggers if SCL stays low for a duration given by TLLO. TLLO is programmable using Settings:Configuration:I2C Config[I2CLLTOT2:0] as 0x0 = timeout is disabled, 0x1 = 0.5 sec, 0x2 = 1 sec, 0x3 = 1.5 sec, 0x4 = 2 sec, 0x5 = 2.5 sec, 0x6 = 3 sec, 0x7 = 3.5 sec. To use this timeout, Settings:Configuration:I2C Config[I2CLLTO] must be cleared.

An I²C write transaction is shown in I²C Write. Block writes are allowed by sending additional data bytes before the Stop. The I²C logic auto-increments the register address after each data byte. The shaded regions show when the device can clock stretch.

Figure 8-1 I²C Write

The CRC check is enabled by setting the Settings:Configuration:I2C Config[CRC] data memory bit. When enabled, the CRC is calculated as follows:

• The CRC is reset after each data byte and after each stop.
• In a single-byte write transaction, the CRC is calculated over the target address, register address, and data.
• In a block write transaction, the CRC for the first data byte is calculated over the target address, register address, and data. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x⁸ + x² + x + 1, and the initial value is 0.

When the target detects an invalid CRC, the I²C target NACKs the CRC, which causes the I²C target to go to an idle state.

I²C Read with Repeated Start shows a read transaction using a Repeated Start. The shaded regions show when the device can clock stretch.

Figure 8-2 I²C Read with Repeated Start

I²C Read without Repeated Start shows a read transaction where a Repeated Start is not used, for example if not available in hardware. For a block read, the controller ACKs each data byte except the last and continues to clock the interface. The I²C block auto-increments the register address after each data byte. The shaded regions show when the device can clock stretch.

Figure 8-3 I²C Read without Repeated Start

When enabled, the CRC for a read transaction is calculated as follows:

• The CRC is reset after each data byte and after each stop.
• In a single-byte read transaction using a repeated start, the CRC is calculated beginning at the first start, so includes the target address, the register address, then the target address with read bit set, then the data byte.
• In a single-byte read transaction using a stop after the initial register address, the CRC is reset after the stop, so only includes the target address with read bit set and the data byte.
• In a block read transaction using repeated starts, the CRC for the first data byte is calculated beginning at the first start and includes the target address, the register address, then the target address with read bit set, then the data byte. The CRC for subsequent data bytes is calculated over the data byte only.
• In a block read transaction using a stop after the initial register address, the CRC is reset after the stop, so only includes the target address with read bit set and the first data byte. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x⁸ + x² + x + 1, and the initial value is 0.

When the controller detects an invalid CRC, the I²C controller NACKs the CRC, which causes the I²C target to go to an idle state.