SLVAE09B July   2018  – August 2021 TPS560430

 

  1.   Trademarks
  2. 1Introduction
  3. 2Peak Current Mode Loop Modeling
    1. 2.1 Overall Control Block Diagram and Transfer Function Derivation
    2. 2.2 Inside Current Loop Model
    3. 2.3 Overall Loop Model
    4. 2.4 Inductor and Output Capacitor Design Limits
    5. 2.5 The Equation to Calculate Bandwidth and Phase Margin
  4. 3Inductor and Output Capacitor Design
    1. 3.1 Inductor Design
    2. 3.2 Output Capacitor Design
    3. 3.3 Simulation and Bench Verification
  5. 4Summary
  6. 5References
  7. 6Revision History

3 Inductor and Output Capacitor Design

In this section, the inductor and output capacitor is designed in a practical application using TPS560430XF. The loop response is considered during the process. Table 3-1 lists the design specifications.

Table 3-1 Design Example Specification
VIN (V)VO (V)IO (A)IO_min (A)fSW (kHz)OUTPUT RIPPLE (mV)VREF (V)
7 V to 36 V, typical 12 V50.60.11100< 301