SLVAEO4 March   2020 TPS6521815 , TPS6521835

 

  1.    System Power Block Diagram
  2.    TI Tech Note
  3.    References
    1. 0.1 Trademarks

TI Tech Note

Can you change PMICs?

Using a multi-rail power management IC (PMIC) for an applications processor is common, but typically the vendor recommends the PMIC that should be used for each processor. Even if the suggested PMIC is not ideal for the needs of the processor, often the complexity makes it difficult to swap out the PMIC for another solution. The purpose of this tech note is to show that the TPS6521815 PMIC can provide power for the i.MX 6ULL and 6UltraLite processors.

Why the TPS6521815?

The TPS6521815 device has an input range from 2.7 to 5.5 V, making it appropriate for system-on-module applications powered from a 3.3-V or 5-V DC supply or a Li-Ion battery. The device has four step-down converters that provide the following: 1.28-V power rail with DVS required for the ARM® and SoC cores, 1.35-V (or 1.5-V) rail required for DDR3L (or DDR3) memory, 1.8-V and 3.3-V rails required for I/Os. A low-dropout (LDO) regulator provides 2.8-V for LCD screen I/O. The TPS6521815 automatically sequences these rails in the correct power-up sequence for the i.MX 6ULL and 6UltraLite processors.

How do you make the switch?

The TPS6521815 output voltages and sequencing order are determined by an EEPROM-backed register map, which can be programmed using the BOOSTXL-TPS65218 socketed booster pack. Samples of the TPS6521815RSLR can be programmed during the prototype phase of product development and soldered down on the TPS65218EVM-100 or the prototype PCB of the final product to evaluate the performance of the PMIC. To order pre-programmed samples of the TPS6521815RSLR for the NXP i.MX 6ULL, 6UltraLite processor that match this tech note, contact the programming services organization at ARROW.

Table 1. i.MX 6ULL and 6UltraLite Power Requirements

TPS6521815 i.MX 6ULL/6UltraLite
POWER-UP SEQUENCE POWER SUPPLY (OUTPUT) OUTPUT CURRENT [mA] OUTPUT VOLTAGE [V] POWER SUPPLY (INPUT) VOLTAGE RATING [V] MAX CURRENT(3) [mA]
1 DCDC1 1800 1.28 / 1.33(2) VDD_SOC_IN
(for VDD_SOC, VDD_ARM)		 Minimum: 1.275 / 1.325
Maximum: 1.5		 500
2 DCDC2 1800 1.35 (or 1.5) NVCC_DRAM Minimum: 1.283
Typical: 1.35
Maximum: 1.45 		124 – 291
3 DCDC3 1800 3.3 VDD_HIGH_IN(1) Minimum: 2.8
Maximum: 3.6 		125
3 DCDC4 1600 1.8 NVCC_1V8 Minimum: 1.65
Maximum: 3.6		 Maximum IO current
5 LDO1 400 2.8 LCD screen (IOVDD) Minimum: 1.65
Maximum: 3.3 		15
0 DCDC6(4) 25 2.5 VDD_SNVS_IN Minimum: 2.4
Maximum: 3.6 		0.5
4 LS1 350 3.3 VDDA_ADC_3P3, NVCC_3V3 Minimum: 3.0
Maximum: 3.6 		35 + Maximum IO current
N/A LS2, LS3 920, 900 5 USB_OTGx_VBUS Minimum: 4.4
Maximum: 5.5		 50 each + USB device current
(1) LDO_2P5 and LDO_1P1 internal LDO regulators are enabled to generate voltages for all NVCC power inputs not using 3.3 V or 1.8 V
(2) This set-point is based on the use case where the LDO (which generates VDD_ARM_CAP and VDD_SOC) is enabled. The voltage can be modified by the processor after power-on using I2C, a feature named dynamic voltage-frequency scaling (DVS or DVFS) such that VDD_SOC_IN is 125 mV greater than the LDO output set-point.
(3) The maximum current for VDD_SOC_IN (VDD_ARM and VDD_SOC core rails) is from the Maximum Supply Currents table in the IMX6ULLIEC and IMX6ULIEC data sheets. Other maximum currents values are from the same source, from AN5345 application note, or estimates including I/O calculation and peripheral current consumption.
(4) DCDC6 has direct feedback to a reference of 1.8 V, allowing the use of a resistor divider to generate the correct voltage for VDD_SNVS

Table 2. Adjacent Tech Notes

Processor Title
i.MX 6Solo and 6DualLite Powering the NXP i.MX 6Solo, 6DualLite Processor with the TPS6521815 PMIC
i.MX 7Solo and 7Dual Powering the NXP i.MX 7 Processor with the TPS6521815 PMIC
i.MX 8M Mini and Nano Powering the NXP i.MX 8M Mini and Nano with the TPS6521825 and LP873347 PMICs