On the ADC12DJ5200 evaluation module, an RF PLL is used as a frequency synthesizer for clocking the ADC. Similar to high speed ADCs, higher frequencies command larger supply currents. At the same time, higher frequencies require lower clock jitter and therefore lower phase noise. Phase noise is directly impacted by the power supply noise and ripple. Since the LMX is powered from a 3.3-V supply rail, the PSRR is measured from the 3.3-V rail to the spurs of the output specturm. The LMX PSRR has a low-pass behavior with increasing attenuation at frequencies above the PLL loop bandwidth. The most sensitive frequency range for supply noise is before and around the PLL corner frequency, and heavily depends on the PLL filter characteristics. At low frequencies the noise is dominated by the external oscillator noise. Therefore, it is key to have a low-noise DC-DC converter design with <20 μV_RMS noise (100 Hz to 100 kHz) and low spectral noise density of ~0.1 uV/√(Hz) before the PLL corner frequency in the range of 1kHz to 100kHz to achieve clock jitter of 100 fs and lower. The performance of the TPS62913 is shown in Figure 1-3.

The TPS62913 has been designed specifically for low noise with the addition of an external noise reduction filter cap, which also provides the means to adjust the softstart time. Using a 470 nF C_NR/SS cap provide the noise performance desired and a 5 ms softstart time.