SLVAFC0 February   2022 TPS272C45

 

  1.   Trademarks
  2. 1Introduction
  3. 2PCB Hardware Modifications for 60-V Tolerance
  4. 360-V Tolerance Test
  5. 4Surge Test Results
  6. 5Inductive Load Test
  7. 6Summary

Surge Test Results

Surge tests have been performed on TPS272C45C to ensure the robustness of the device. The surge waveform demonstrated in Figure 4-1 follows the IEC61000-4-5 standard at 1 kV with 42 Ω impedance. The 42 Ω impedance represents the impedance between all other lines and GND IEC 61000-4-x Tests for TI’s Protection Devices application report.

GUID-20220124-SS0I-3HRG-JJTV-HQQFHBQJGFLW-low.png Figure 4-1 Surge Waveform on Resistive Load

Both positive and negative surges have been performed at VS and VOUT, and the two surge test setups are shown in Figure 4-2 and Figure 4-3.

Figure 4-2 Positive Surge Setup
Figure 4-3 Negative Surge Setup

At first, the positive surge is applied on 24-V VS with EN high for both channels and a 12 Ω load connected at the output. The waveform is shown in Figure 4-4. The VS is clamped by the VS to GND TVS diode D2 during the surge event, and it will absorb the majority of the surge energy. The device goes back to the normal operation after the surge.

GUID-20220124-SS0I-QKMH-NB6T-R2RVFPXQW2V2-low.pngFigure 4-4 Waveform with Positive Surge Applied on VS

The second test involves a negative surge being applied to VS with the same setup. The resulting waveform is shown in Figure 4-5. In this case, the VS to GND diode D2 is conducting and keeping VS at the ground level during the negative surge. The device is operating as expected and kept on after the VS recovers.

GUID-20220124-SS0I-K62P-DJHF-GX5BFM702GK6-low.pngFigure 4-5 Waveform with Negative Surge Applied at VS

Turning now to the test setup demonstrated in Figure 4-3, surges are applied at VOUT with 24 V on the input, EN is high, and 12 Ω is connected to the load. Figure 4-6 shows the resulting waveform when the positive surge is applied. During the surge, the body diode will be conducting, and the diode from VS to GND will clamp the VS voltage. As current keeps flowing in the decoupling inductor, the voltage at Vs will remain high for a short duration and slowly recovers.

GUID-20220124-SS0I-ZQ5R-9BJZ-6QHDP7T3M5VS-low.pngFigure 4-6 Waveform with Positive Surge Applied at VOUT and EN is High

Figure 4-7 shows the resulting waveform when the negative surge is applied to VOUT. The VS to GND TVS diode is conducting, which takes VS to the GND level. The supply and FET operation resumes normal operation after the surge pulse is over.

GUID-20220124-SS0I-2HCZ-NK1H-LKZMF5SV2B8M-low.pngFigure 4-7 Waveform with Negative Surge Applied at VOUT and EN is High

The same surge tests are performed at VOUT while EN is low. With a positive surge at VOUT, Figure 4-8 shows that the TVS diode from VOUT to VS is conducting, and then VS voltage is clamped by the other TVS diode. The device is kept off after the surge event.

GUID-20220124-SS0I-HGLX-HQ9K-HHLVBKT9LJGJ-low.pngFigure 4-8 Waveform with Positive Surge Applied at VOUT and EN is Low

When the negative surge is applied at VOUT with EN low, Figure 4-9 shows the behavior where the VS to GND diode is conducting and the VS to VOUT diode is clamping. The device remains off after the surge pulse as expected.

GUID-20220124-SS0I-MDNC-TS0J-K3KDGJQRJBCZ-low.pngFigure 4-9 Waveform with Negative Surge Applied at VOUT and EN is Low