2 What are PSYS™ and PSYS_CRIT#™?

In multi-phase voltage regulator (VR) systems, system input power is delivered at a single nominal voltage level. This voltage can be supplied by a single PSU or by multiple redundant PSUs connected in parallel. A simplified block diagram is shown in Figure 2-1.

Figure 2-1 Simplified Block Diagram: Voltage Regulator (VR) Systems

The PSU can be either an AC/DC supply or a bus bar from a rack-level power supply. The VR14 controller computes system input power from input current (ISYS) and voltage (VSYS) signals. Even at the very highest power levels, the system input voltage, VSYS, is assumed to be nearly constant. At peak PSU output, VSYS can have a predictable droop. System input power is computed via the product of ISYS and VSYS. This power monitoring functionality is called PSYS™ and is used for the manipulation of CPU performance by taking advantage of available surplus average (and, in some instances, peak) energy.

The PSYS interconnection block diagram is shown in Figure 2-2. It illustrates the location of the PSYS monitor, which is typically located near the input power source connector(s) or PSU and the VR14 PWM controller. These are situated at the opposite ends of a platform assembly. This helps improve the noise immunity of the analog signal used to track input power, in this case, PSU current, or ISYS.

Figure 2-2 Simplified Diagram of the PSYS Interconnection

VSYS and ISYS are tracked separately, digitized, and multiplied in the VR14 PWM controller to obtain the PSYS digital output, as shown in Figure 2-3(a). Alternatively, VSYS and ISYS are multiplied in real time in the analog domain, and the result is digitized to obtain the PSYS digital output, as shown in Figure 2-3(b). Both approaches are valid if the digital PSYS output accuracy expectations are met.

Figure 2-3 Implementation of the Digital PSYS™ in VR14 Controller

ISYS: To improve noise immunity, PSU current information is required to be represented using a current proportional to the current observed at the sensor. The ways to generate the ISYS output are described in detail in Section 3.

VSYS: It is the voltage at the input to the platform, near the output of the PSU(s). VSYS is used to convert the ISYS information into PSYS in watts. VSYS needs to be sensed near the PSYS monitor or PSU to consider the voltage drops across the platform. If it is required to implement a resistor divider to bring the magnitude of the input voltage down to the acceptable levels of the VSYS pin in the VR controller, tight tolerance resistors (± 0.1%) are recommended to meet the PSYS accuracy requirements.

An over-stressed PSU can enter fold-back constant power mode. Observing power instead of current can not indicate to the VR14 controller the magnitude at which the PSU is being stressed. Therefore, ISYS is used as the main measurement parameter here. Another benefit of an analog ISYS-measured system is the potential aggregation of several PSYS monitor outputs.

VR14 PWM Hardware Alarms (for example, VR_HOT#™ and PSYS_CRIT#™) are needed to handle peak power events; otherwise, that can cause local voltage regulators to over-heat or damage the power supplies. Both the VR_HOT#™ and PSYS_CRIT#™ are open drain logics, active low, and are used to drive the processor’s force thermal throttle input (PROCHOT#™). The VR_HOT#™ asserts when the temperature sensed by the VR controller exceeds a pre-programmed threshold (TMAX) value. The detailed implementation and functionality are not discussed in this document.

Hardware alarms are the last line of defense for systems that attempt to operate at near hardware peak power limits. This helps eliminate the requirement of over-designing the systems to handle severe (for example, much larger in magnitude than thermal design power) peak power events.

Digital versions of PSYS are useful for the monitoring of average power events. Digital PSYS is a poor indicator of peak power events. Because the time taken to digitize the VSYS and ISYS signals and multiply them to generate PSYS digital output and then react to a peak power event is beyond the input power handling capability of a generic PSU.

VR14 controller allows for monitoring peak power events. PSYS_CRIT#™ is an active low, open drain logic derived from the ISYS data to drive the processor’s force thermal throttle input. The differences between VR_HOT#™ and PSYS_CRIT#™ are as follows:

• In a multi-CPU system, VR_HOT#™ is implemented in each VR14 controller by sensing their own temperature. Whereas PSYS_CRIT#™ is implemented only in one VR14 controller connected to a CPU, suppose CPU0, by sensing the total platform current drawn by the multiple CPUs and other loads.
• Each VR_HOT#™ assertion (low) only throttles the power consumption of the associated CPU, not all the CPUs. Whereas the assertion of PSYS_CRIT#™ throttles the power consumption of all the CPUs drawing power from the PSU.

The preferred method of PSYS_CRIT#™ alarm implementation is at the VR14 PWM controller level, not the PSYS monitor level. The VR14 controller implements the PSYS_CRIT#™ functionality in two ways.

• The analog ISYS signal is fed to a high-speed analog comparator to trigger the assertion of PSYS_CRIT#™ output once a threshold of current is exceeded, as shown in Figure 2-4(a).
• The digitized ISYS data is fed to a high-speed digital comparator to trigger the assertion of PSYS_CRIT#™ output once a threshold of current is exceeded, as shown in Figure 2-4(b).

Figure 2-4 Implementation of the PSYS_CRIT#™ in VR14 Controller