SLVAFH6 November 2023 LM25066 , LM5066 , LM5066I , TPS25984 , TPS25985 , TPS25990 , TPS536C9T

5 Functional Verification of PSYS and PSYS_CRIT# in TPS536C9T VR14 Controller Using TPS25984, TPS25985, or TPS25990 eFuses as PSYS Monitor

Figure 5-1 presents the basic interconnection block diagram for implementing PSYS™ and PSYS_CRIT#™ in TPS536C9T VR14 controller using TPS25984, TPS25985, or TPS25990 eFuses.

ISYS_IN: ISYS input, full-scale range of 1.8 V,
VSYS_IN: VSYS input, recommended range of 4.5 V to 17 V,
PSYS_CRIT#: VR14 PSYS alert, open drain output, recommended range of - 0.1 V to 3.6 V,

Figure 5-1 Interconnection Block Diagram Between eFuse and VR14 Controller in Implementing Digital PSYS™ and PSYS_CRIT#™

Figure 5-2 represents a snapshot of the digital PSYS output captured from the Fusion Digital Power™ Graphical User Interface (GUI) using TPS536C9T controller. ISYS and Digital PSYS are obtained to be 1.6% and 1.7% accurate, respectively, whereas the target specification is 2%.

Figure 5-2 Digital PSYS

The PSYS_CRIT#™ threshold is set in the SVID register as a fraction of the maximum transient input current capability of the PSU. The threshold register contains a linear fraction of the corresponding to the telemetry input’s full-scale value. The assertion of PSYS_CRIT#™ while the input current, in other words, the voltage at the ISYS pin in the TPS536C9T controller exceeds the pre-programmed threshold in SVID. The PSYS_CRIT#™ threshold in normal resolution telemetry is defined in Equation 7.

Equation 7.

D i g i t a l_P S Y S_C R I T #_T h r e s h o l d (8 b i t, d e c i m a l) = T r u n c a t e [\frac{2^{8} \times A n a l o g_P S Y S_C R I T #_T h r e s h o l d (A)}{F u l l_S c a l e (A)}];

Q u a n t i z e d_A n a l o g_P S Y S_C R I T #_T h r e s h o l d (A) = [\frac{F u l l_S c a l e (A) \times D i g i t a l_P S Y S_C R I T #_T h r e s h o l d (8 b i t, d e c i m a l)}{2^{8}}]

The time delay in asserting the PSYS_CRIT#™ is depicted in fontoxml-text-placeholder text="Type the link text". The maximum delay contributed by the TPS25984, TPS25985, or TPS25990 eFuses in monitoring the PSU current (or platform current) is less than 500 ns, as shown in Figure 3-6. Therefore, the total delay between exceeding the PSU current beyond the pre-programmed threshold and the assertion of PSYS_CRIT# in the TPS536C9T controller is 5.5 μs, whereas the PSYS specifications require 10 μs.

Given Analog_PSYS_CRIT#_Threshold as 73 A, Full_Scale as 252 A, and using Equation 7, the Digital_PSYS_CRIT#_Threshold (8 bit, decimal) is calculated to be 74, in hexadecimal 4Ah. This hexadecimal data is written into a specified SVID resister to assert the PSYS_CRIT# when the input current to the power stages exceeds 73 A. Figure 5-4 illustrates the assertion and de-assertion of PSYS_CRIT#, implemented in the TPS536C9T VR14 controller using TPS25990 as the PSYS monitor.

Figure 5-3 PSYS_CRIT# Assertion Delay in the TPS536C9T Controller

Figure 5-4 Assertion of the PSYS_CRIT# TPS536C9T Controller Using TPS25990 as the PSYS monitor