SLVAFP8 December   2023 AM625SIP , TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 TPS65219 Overview
    1. 2.1 TPS65219 Functional Block Diagram
  6. 3 TPS65219 Variants
    1. 3.1 TPS65219 NVMs to Power AM625SIP
  7. 4 TPS6521905 User-Programmable NVM
  8. 5 AM62x Core Voltage Selection
  9. 6 VSYS Voltage Ramp
  10. 7 Power Block Diagrams
    1. 7.1 TPS6521902 Powering AM62x
    2. 7.2 TPS6521908 Powering AM62x
  11. 8 TPS65219 VS Discrete
  12. 9 Summary
  13. 10References

7 Power Block Diagrams

There are several considerations to take into account when designing the TPS65219 to power the AM62 processor and the peripherals.

  • Will the application be using LPDDR4 or DDR4 memory?
  • Does an SD card need to be supported?
  • What will the system supply voltage be?
  • Are there any external discrete ICs that will require fully controlled sequencing?
  • Does system application prioritize highest integration or lowest power consumption?

Each of these questions impact the design, configuration, setup, among others, of the power block diagram and plays a role designing the most robust power solution. The sections below describe how the TPS65219 PMIC can supply the AM62x processor on different application requirements.

All the TPS65219 variants described in this application note have LDO1 configured as bypass to supply the SD card dual-voltage I/O (3.3 V and 1.8 V). A processor GPIO control signal with a logic high default value and an external pull-up is used to set SD IO to 3.3 V initially. After the power-up sequence, the processor can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This bypass configuration allows control of the LDO1 voltage from 3.3 V to 1.8 V without the need to establish I2C communication during boot from SD card operations. The bypass configuration on LDO1 requires connecting its input supply pin (PVIN_LDO1) to 3.3 V.