SLVAFP9 October   2024 TPS65219 , TPS6521905

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS65219 Overview
  6. 3Power Delivery Networks
    1. 3.1 Always ON: Designed for Cost (-1 and -2 Devices)
    2. 3.2 Always On: Designed for Power and or Efficiency (-1L and -2L Devices)
    3. 3.3 Always On: Designed for PL Performance (-3 Devices)
    4. 3.4 Full Power Management Flexibility (All Speed Grade)
  7. 4Loading a NVM Configuration File to PMIC
  8. 5Summary
  9. 6References

1 Introduction

Xilinx’s Zynq UltraScale+ MPSoC line offers a high level of flexibility, with a range of devices that scale in complexity to work with a wide variety of applications. As such, the designs that power the Zynq UltraScale+ must be equally adaptable to meet the power needs of a complex line. This application note describes how TI’s user programmable TPS6521905 Power Management IC (PMIC) can be configured to meet the power requirements of the Xilinx® Zynq® UltraScale+®. The MPSoC integrates independent power domains that can be isolated for low power mode implementation, reducing the overall power consumption. When applications do not require the use of low power modes, the power domains can also be combined, reducing the amount of rails that are needed and allowing to reduce the BOM size/cost of the power design.

PMIC and SoC data sheets provide recommended operating conditions, electrical characteristics, recommended external components, package details, register maps, and overall component functionality. In the event of any inconsistency between any user's guide, application report, or other referenced material, the data sheet specification is the definitive source.