SLVAFP9 October   2024 TPS65219 , TPS6521905

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS65219 Overview
  6. 3Power Delivery Networks
    1. 3.1 Always ON: Designed for Cost (-1 and -2 Devices)
    2. 3.2 Always On: Designed for Power and or Efficiency (-1L and -2L Devices)
    3. 3.3 Always On: Designed for PL Performance (-3 Devices)
    4. 3.4 Full Power Management Flexibility (All Speed Grade)
  7. 4Loading a NVM Configuration File to PMIC
  8. 5Summary
  9. 6References

3.1 Always ON: Designed for Cost (-1 and -2 Devices)

The always ON/cost designed power supply consolidation uses the -1/-2 speed grade devices. This power scheme allows to consolidate the 0.85V domains. When VCCINT and VCCINT_IO/VCCBRAM operate at the same voltage levels, they can be powered by the same supply and ramped simultaneously. If the maximum total current of all the power domains supported by External1 and the PMIC DCDC1 does not exceed 3.5A, all these domains can be supplied by DCDC1. Alternatively, all the 0.85V domains can be supplied by the External1 and the DCDC1 from the PMIC can be re-programmed to supply other power domains in the application.

Note: If all the 0.85V domains are supplied by External1, the PMIC Buck1 can be re-programmed to output 3.3V and used to supply the PMIC LDOs to help reduce the power consumption.
Designed for Cost (-1 and -2 Devices) PDNFigure 3-1 Designed for Cost (-1 and -2 Devices) PDN
Note: Designed for Cost (-1 and -2 Devices): TPS6521905 PMIC NVM configuration file link.
Designed for Cost (-1 and -2 Devices) Power-Up SequenceFigure 3-2 Designed for Cost (-1 and -2 Devices) Power-Up Sequence
Always ON: Designed for Cost (-1 and -2 Devices) Power-Down SequenceFigure 3-3 Always ON: Designed for Cost (-1 and -2 Devices) Power-Down Sequence