SLVAFP9 October   2024 TPS65219 , TPS6521905

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS65219 Overview
  6. 3Power Delivery Networks
    1. 3.1 Always ON: Designed for Cost (-1 and -2 Devices)
    2. 3.2 Always On: Designed for Power and or Efficiency (-1L and -2L Devices)
    3. 3.3 Always On: Designed for PL Performance (-3 Devices)
    4. 3.4 Full Power Management Flexibility (All Speed Grade)
  7. 4Loading a NVM Configuration File to PMIC
  8. 5Summary
  9. 6References

3.3 Always On: Designed for PL Performance (-3 Devices)

The Always ON-Programmable Logic (PL) performance designed for power consolidation supports the highest PL performance and uses -3 speed grade devices. In this power scheme, all the core rails (VCCINT, VCCINT_VCU, VCCBRAM, VCCINT_IO, VCC_PSINTLP, VCC_PSINTFP, and VCC_PSINTFP_DDR) are run at a nominal voltage of 0.9V.

Designed for PL Performance (-3 Devices) PDNFigure 3-7 Designed for PL Performance (-3 Devices) PDN
Note: Designed for PL Performance (-3 Devices): Please request TPS6521905 PMIC NVM configuration file on the TI Power Management E2E forum.
Designed for PL Performance (-3 Devices) Power-Up SequenceFigure 3-8 Designed for PL Performance (-3 Devices) Power-Up Sequence
Designed for PL Performance (-3 Devices) Power-Down SequenceFigure 3-9 Designed for PL Performance (-3 Devices) Power-Down Sequence