SLVAFP9 October   2024 TPS65219 , TPS6521905

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS65219 Overview
  6. 3Power Delivery Networks
    1. 3.1 Always ON: Designed for Cost (-1 and -2 Devices)
    2. 3.2 Always On: Designed for Power and or Efficiency (-1L and -2L Devices)
    3. 3.3 Always On: Designed for PL Performance (-3 Devices)
    4. 3.4 Full Power Management Flexibility (All Speed Grade)
  7. 4Loading a NVM Configuration File to PMIC
  8. 5Summary
  9. 6References

TPS65219 Overview

The TPS65219 is a cost and space optimized PMIC. TPS65219 integrates 3 Buck regulators, 4 Low Drop-out Regulators (LDO), GPIO, multi-function pins and I2C communication. The power and digital resources can be configured to meet the requirements of a variety of applications. The GPIO can be configured to enable or disable external discrete ICs when needed. This device has two package options: 4mm × 4mm 0.4m pitch VQFN package or 5mm × 5mm 0.5m pitch VQFN package. Table 2-1 shows a summary of the power resources.

The TPS6521905 is the user programmable version that comes with all Bucks and LDOs disabled by default to provide freedom to customize the desired output voltages, sequencing and more from start up to fit the system needs. For applications that require 7+ rails, this PMIC also offers a multi-PMIC configuration which allows to synchronize the sequence of 2x TPS65219 devices. The small package options, the highly integrated resources and configuration flexibility makes the TPS65219 PMIC a full power package to supply the Zynq UltraScale+ for the largest range of ZU+ devices, from ZU2CG all the way through ZU19EG. For more information on the different ZU+ devices, please refer to the Xilinx Zynq UltraScale+ site. Table 2-2 shows a summary of the main available resources to assist with the design process and the PMIC NVM programming. For any questions or technical support, use the Power Management E2E design support forum.

Table 2-1 TPS65219 Power Resources
Input Voltage Output Voltage Current Capability Comments
BUCK1 2.5V - 5.5V 0.6V - 3.4V 3.5A
  • 2.3MHz switching frequency (auto-PFM or forced-PWM)
  • Dynamic voltage scaling
  • Configurable bandwidth. Low bandwidth for a smaller output capacitance (lower cost) or high bandwidth to support higher transient (higher performance).
  • Programmable power sequencing and default voltages.
  • Integrated voltage supervisor for undervoltage and current limit.
BUCK2 2.5V - 5.5V 0.6V - 3.4V 2A
BUCK3 2.5V - 5.5V 0.6V - 3.4V 2A
LDO1 1.5V - 5.5V (LDO, Load-Switch)

1.5V - 3.4V (Bypass)

0.6V - 3.4V (LDO)

1.5V - 3.4V (Bypass)

400mA
  • Programmable power sequencing and default voltages.
  • Configurable as LDO, load switch or bypass-mode.
  • Integrated voltage supervisor for undervoltage and current limit
LDO2 1.5V - 5.5V (LDO, Load-Switch)

1.5V - 3.4V (Bypass)

0.6V - 3.4V (LDO)

1.5V - 3.4V (Bypass)

400mA
LDO3 2.2V - 5.5V 1.2V - 3.3V 300mA
  • Programmable power sequencing and default voltages.
  • Configurable as LDO or load switch
  • Integrated voltage supervisor for undervoltage and current limit.
LDO4 2.2V - 5.5V 1.2V - 3.3V 300mA
Table 2-2 TPS6521905 Programming Resources
Resources Links
Programming Guide TPS65219 Non-Volatile Memory (NVM) Programming Guide
Graphical User Interface (GUI) TPS65219 graphical user interface
Socketed EVM TPS65219 non-volatile memory (NVM) programming board
Programming Tutorial Video Programming the TPS6521905
TPS6521905 data sheet User-programmable power management IC (PMIC) with three step-down DC/DC converters and four LDOs