The Full Power Management flexibility can be supported with all the speed grade devices. This power scheme significantly reduces the power domain consolidation but allows to use ultra-low power states to reduce overall power consumption and/or maximize battery life. Figure 3-10 shows the TPS65219 multi-PMIC configuration + discrete ICs to powering Xilinx Zynq UltraScale+. This PDN shows how the application can isolate the four independent domains (LPD, FPD, PLPD and BPD) to disable specific power rails when unused.

Figure 3-10 Full Power Management PDN

Figure 3-11 Full Power Management - Power-Up Sequence

Figure 3-12 Full Power Managements - Power-Down Sequence