SLVAFS9 August 2024 DRV8316 , DRV8317
Based on the data provided in the previous section, this application note presents several recommendations for designers needing to maximize the thermal performance and efficiency of the integrated FET driver. First, within groups of equivalent power-level motor drivers, the integrated FET driver with the lowest Rds(on) value reduces conduction losses, which dominate total power loss at high current outputs. Second, to facilitate current output near the maximum of the device, TI recommends using a reasonable switching frequency based on the motor type with the highest slew rate possible that does not introduce EMI issues. Lastly, based on the diode loss equations, use as small a dead time as possible that still prevents cross-conduction events. These settings can reduce the overall temperature of the device at a given current, meaning the device can be able to reach higher current output before triggering an overtemperature shutoff (note that these devices are still limited by an overcurrent threshold). However, some systems can be susceptible to EMI due to ringing nodes caused by high slew rates, so designers must always be aware of the tradeoffs to create a robust system. Although not presented in this application note, current output from internal voltage regulators can also generate heat through added power loss. To reduce this power loss, avoid drawing significant current from these regulators in the rest of the circuit. Lowering the voltage input to these regulators can also reduce power loss by decreasing the voltage drop that needs to be made for the regulated output; however, split power supplies is not an available feature in every device. Refer to the data sheet for more information. Users can also refer to another application note on layout best practices.
Additionally, a thermally-optimized PCB design can significantly help with heat dissipation. The ground pad on the bottom of the device package needs to be connected to as much unimpeded copper as possible on several layers. Using simulated calculations from the available integrated FET driver thermal calculators available on ti.com, a small area of copper on a two-layer PCB results in a higher junction temperature than a large copper area on a four-layer PCB. The copper area needs to extend around the device as much as possible, with very few interruptions from routed traces, vias, or other components. Thermal vias must be used to stitch ground planes on one layer to another, and the vias need to be used extensively on the ground pad of the device footprint.
Another strategy for increasing the size of the copper ground plane around the device is to unify PGND and AGND into one solid ground plane, rather than attaching separate planes through a net tie. Users need to make sure that large current return paths do not cross directly under the device in the layout. However, this can create noise in the current sense amplifiers (if the current sense amplifiers are integrated in the driver, such as in the DRV8316 and DRV8317) and cause possible inefficiencies in sensorless commutation algorithms that use current monitoring. Finally, the copper connections between the motor driver and each phase output port needs to be as wide as possible, both to accommodate the large amounts of current and to provide additional routes for thermal dissipation.
Lastly, when testing the system’s thermal performance, remember to keep these considerations in mind while working with integrated FET drivers: