SLVK172 June   2024 TPS7H3014-SP

 

  1.   1
  2.   TPS7H3014-SP Single-Event Effects (SEE)
  3.   Trademarks
  4. Introduction
  5. Single-Event Effects (SEE)
  6. Device and Test Board Information
  7. Irradiation Facility and Setup
  8. Depth, Range, and LETEFF Calculation
  9. Test Setup and Procedures
  10. Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-Up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. Single-Event Transients (SET)
  12. Event Rate Calculations
  13. 10Summary
  14.   A References

Single-Event Effects (SEE)

The primary concern for the TPS7H3014-SP is the robustness against the destructive single-event effects (DSEE): single-event latch-up (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H3014-SP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1, 2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the device is destroyed by the high-current state. During the testing of the TPS7H3014 a total of three units were exposed under worst-case bias conditions for SEL. The TPS7H3014-SP did not exhibit any SEL with heavy-ions with LETEFF = 75MeV·cm2 /mg at flux of ≈8 × 104 ions/cm2 ·s, fluence of ≈107 ions/cm2, and a die temperature of 125°C.

The TPS7H3014-SP was evaluated for SEB/SEGR at a maximum voltage of 14V (VIN) in the waiting to sequence up (all outputs low) and waiting to sequence down (all outputs high) states. Because it has been shown that the MOSFET susceptibility to burnout decrement with temperature [5], the device was evaluated while operating under room temperatures. The device was tested with no external thermal control device. During the SEB/SEGR testing, not a single current event was observed, demonstrating that the TPS7H3014-SP is SEB/SEGR-free up to LETEFF = 75MeV·cm2/mg at a flux of ≈8 × 104 ions/cm2·s, fluence of ≈107 ions/cm2, and a die temperature of ≈25°C.

The TPS7H3014-SP was tested under nominal input conditions for SET. During the testing of three devices, not a single transient was recorded, showing that the TPS7H3014-SP is both transient free and SEFI free. To see more details please refer to Section 8.

The forcing conditions for the different DSEE and SET testing are shown in Table 2-1.

Table 2-1 SEE Biasing Conditions
DSEE TYPEVIN (V)VPULL_UP (V)VUP (V)TJ (°C)FLUX

(ions/cm2·s)

FLUENCE

(ions/cm2)

SEL

14

7

3

125

5 × 104/run

107/run

SEB/SEGR

14

7

3

25

SET

[5,12]

3.3

[0,1]

25