SLVS416C February   2002  – January  2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Dissipation Ratings
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Lock Out (UVLO)
      2. 7.3.2  Slow-Start/Enable (SS/ENA)
      3. 7.3.3  VBIAS Regulator (VBIAS)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Oscillator and PWM Ramp
      6. 7.3.6  Error Amplifier
      7. 7.3.7  PWM Control
      8. 7.3.8  Dead-Time Control and MOSFET Drivers
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Powergood (PWRGD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Switching Frequency Selection/Synchronization
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection
        2. 8.2.2.2 Input Voltage
        3. 8.2.2.3 Feedback Circuit
        4. 8.2.2.4 Operating Frequency
        5. 8.2.2.5 Output Filter
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
        1. 11.1.1.1 Related DC - DC Products
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS5431x devices are 3-V to 6-V integrated FET synchronous buck converters. They are used to convert a DC input voltage on the VIN pins to a lower output voltage at 3 A maximum output current.

8.2 Typical Application

Figure 10 shows the schematic diagram for a typical TPS54314 application. The TPS54314 (U1) can provide up to 3 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the PowerPAD underneath the TPS54314 integrated circuit needs to be soldered to the printed circuit board.

TPS54314_Schematic_slvs416.gifFigure 10. TPS54314 Schematic

8.2.1 Design Requirements

The design requirements for this example are listed in Table 3.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
DC Input Voltage Range 3 V – 6 V
DC Output Voltage 1.8 V
DC Output Current Range 0 – 3 A
Output Voltage Ripple 20 mV
Load Transient Output Deviation ±80 mV

8.2.2 Detailed Design Procedure

8.2.2.1 Component Selection

The values for the components used in this design example were selected using the SWIFT designer software tool. SWIFT designer provides a complete design environment for developing dc-dc converters using the TPS54314, or other devices in the SWIFT product family. Additional design information is available at www.ti.com.

8.2.2.2 Input Voltage

The input to the circuit is a nominal 5 VDC, applied at J1. The optional input filter (C2) is a 220-µF POSCAP capacitor, with a maximum allowable ripple current of 3 A. C8 is the decoupling capacitor for the TPS54314 and must be located as close to the device as possible.

8.2.2.3 Feedback Circuit

The output voltage of the converter is fed directly into the VSENSE pin of the TPS54314. The TPS54314 is internally compensated to provide stability of the output under varying line and load conditions.

8.2.2.4 Operating Frequency

In the application circuit, a 700 kHz operating frequency is selected by leaving FSEL open and connecting a 71.5 kΩ resistor between the RT pin and AGND. Different operating frequencies may be selected by varying the value of R3 using Equation 4:

Equation 4. Eq04_R_slvs400.gif

Alternately, a preset operating frequency of 350 kHz or 550 kHz can be selected by leaving RT open and connecting the FSEL pin to AGND or VIN respectively.

8.2.2.5 Output Filter

The output filter is composed of a 5.2-µH inductor and 470-µF capacitor. The inductor is a low-DC resistance (16-mΩ) type, Sumida CDRH104R−5R2. The capacitor used is a 4-V POSCAP with a maximum ESR of 40 mΩ.

The output filter components work with the internal compensation network to provide a stable closed loop response for the converter.

8.2.3 Application Curves

graph_11_slvs416.gifFigure 11. Efficiency vs Load Current
graph_13_slvs416.gifFigure 13. Loop Response
graph_15_slvs416.gifFigure 15. Load Transient Response
graph_17_slvs416.gifFigure 17. Ambient Temperature vs Load Current
graph_12_slvs416.gifFigure 12. Output Voltage vs Load Current
graph_14_slvs416.gifFigure 14. Output Ripple Voltage
graph_16_slvs416.gifFigure 16. Start-Up Waveforms