SLVS974F September   2009  – May 2020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency versus Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation and Output Current
      3. 7.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout
      8. 7.3.8  Soft-Start Pin
      9. 7.3.9  Sequencing
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Frequency Shift
      13. 7.3.13 Reverse Overcurrent Protection
      14. 7.3.14 Synchronize Using the RT/CLK Pin
      15. 7.3.15 Power Good (PWRGD Pin)
      16. 7.3.16 Overvoltage Transient Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Small Signal Model for Loop Response
      2. 7.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 7.4.3 Small Signal Model for Frequency Compensation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Step One: Select the Switching Frequency
        2. 8.2.2.2  Step Two: Select the Output Inductor
        3. 8.2.2.3  Step Three: Choose the Output Capacitor
        4. 8.2.2.4  Step Four: Select the Input Capacitor
        5. 8.2.2.5  Step Five: Minimum Load DC COMP Voltage
        6. 8.2.2.6  Step Six: Choose the Soft-Start Capacitor
        7. 8.2.2.7  Step Seven: Select the Bootstrap Capacitor
        8. 8.2.2.8  Step Eight: Undervoltage Lockout Threshold
        9. 8.2.2.9  Step Nine: Select Output Voltage and Feedback Resistors
          1. 8.2.2.9.1 Output Voltage Limitations
        10. 8.2.2.10 Step 10: Select Loop Compensation Components
        11. 8.2.2.11 Power Dissipation Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.1 Overview

The TPS54218 device is a 6-V, 2-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients, the device implements a constant frequency, peak current mode control that reduces output capacitance and simplifies external frequency compensation design. The wide supported switching frequency range of 200 kHz to 2000 kHz allows efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock.

The TPS54218 device has a typical default start-up voltage of 2.6 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage undervoltage lockout (UVLO) with two external resistors. In addition, the pullup current provides a default condition when the EN pin is floating for the device to operate. The total operating current for the TPS54218 device is 350 μA when not switching and under no load. When the device is disabled, the supply current is less than 5 μA.

The integrated, 30-mΩ MOSFETs allow for high-efficiency power supply designs with continuous output currents up to 2 amperes.

The TPS54218 device reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high-side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54218 device to operate approaching 100%. The output voltage can be stepped down to as low as the 0.8-V reference.

The TPS54218 device has a power-good comparator (PWRGD) with 2% hysteresis.

The TPS54218 device minimizes excessive output overvoltage transients by taking advantage of the overvoltage power-good comparator. When the regulated output voltage is greater than 109% of the nominal voltage, the overvoltage comparator is activated, and the high-side MOSFET is turned off and masked from turning on until the output voltage is lower than 105%.

The SS (soft start) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor must be coupled to the pin for soft start. The SS pin is discharged before the output power up to ensure a repeatable re-start after an overtemperature fault, UVLO fault, or disabled condition.

The use of a frequency-foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help limit the inductor current.