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  • TPS650231 Power Management IC for Li-Ion Powered Systems

    • SLVSAE3A August   2010  – January 2016 TPS650231

      PRODUCTION DATA.  

  • CONTENTS
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  • TPS650231 Power Management IC for Li-Ion Powered Systems
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: Control Signals
    7. 7.7  Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3, VINDCDC13
    8. 7.8  Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
    9. 7.9  Electrical Characteristics: VDCDC1 Step-Down Converter
    10. 7.10 Electrical Characteristics: VDCDC2 Step-Down Converter
    11. 7.11 Electrical Characteristics: VDCDC3 Step-Down Converter
    12. 7.12 Timing Requirements
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  VRTC Output and Operation With or Without Backup Battery
      2. 8.3.2  Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      3. 8.3.3  Power Save Mode Operation
      4. 8.3.4  Low-Ripple Mode
      5. 8.3.5  Soft-Start
      6. 8.3.6  100% Duty Cycle Low-Dropout Operation
      7. 8.3.7  Active Discharge When Disabled
      8. 8.3.8  Power-Good Monitoring
      9. 8.3.9  Low-Dropout Voltage Regulators
      10. 8.3.10 Undervoltage Lockout
      11. 8.3.11 Power-Up Sequencing
      12. 8.3.12 System Reset + Control Signals
        1. 8.3.12.1 DEFLDO1 and DEFLDO2
        2. 8.3.12.2 Interrupt Management and the INT Pin
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register Address: 00h (Read Only)
      2. 8.6.2 PGOODZ Register Address: 01h (Read Only)
      3. 8.6.3 MASK Register Address: 02h (Read or Write), Default Value: C0h
      4. 8.6.4 REG_CTRL Register Address: 03h (Read or Write), Default Value: FFh
      5. 8.6.5 CON_CTRL Register Address: 04h (Read or Write), Default Value: B1h
      6. 8.6.6 CON_CTRL2 Register Address: 05h (Read or Write), Default Value: 40h
      7. 8.6.7 DEFCORE Register Address: 06h (Read or Write), Default Value: 14h/1Eh
      8. 8.6.8 DEFSLEW Register Address: 07h (Read or Write), Default Value: 06h
      9. 8.6.9 LDO_CTRL Register Address: 08h (Read or Write), Default Value: Set with DEFLDO1 and DEFLDO2
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Voltage Connection
      2. 9.1.2 Unused Regulators
      3. 9.1.3 Reset Condition of DCDC1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for Supply Voltages Below 3.0 V
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE
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DATA SHEET

TPS650231 Power Management IC for Li-Ion Powered Systems

1 Features

  • 1.7-A, 90% Efficient Step-Down Converter for Processor Core (VDCDC1)
  • 1.2-A, Up to 95% Efficient Step-Down Converter for System Voltage (VDCDC2)
  • 0.8-A, 92% Efficient Step-Down Converter for Memory Voltage (VDCDC3)
  • 30-mA LDO and Switch for Real-Time Clock (VRTC)
  • 2 × 200-mA General-Purpose LDO
  • Dynamic Voltage Management for Processor Core
  • Preselectable LDO Voltage Using Two Digital Input Pins
  • Externally Adjustable Reset Delay Time
  • Battery Backup Functionality
  • Separate Enable Pins for Inductive Converters
  • I2C™-Compatible Serial Interface
  • 85-μA Quiescent Current
  • Low-Ripple PFM Mode
  • Thermal Shutdown Protection
  • Available in 40-Pin, 5-mm × 5-mm VQFN (RSB) or 49-Ball, 3-mm × 3-mm DSBGA (YFF) Package

2 Applications

  • Smart Phones
  • Netbooks and MIDs
  • Portable Media Players

3 Description

The TPS650231 device is an integrated power management IC for applications powered by one
Li-Ion or Li-Polymer cell, and which requires multiple power rails. The TPS650231 provides three highly efficient step-down converters targeted at providing the core voltage, peripheral, I/O, and memory rails in a processor-based system. The core converter allows for on-the-fly voltage changes through serial interface, allowing the system to implement dynamic power savings.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS650231 VQFN (40) 5.00 mm × 5.00 mm
DSBGA (49) 3.00 mm × 3.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

TPS650231 Keygraphic.gif

4 Revision History

Changes from * Revision (August 2010) to A Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo

5 Description (continued)

All three step-down converters enter a low-power mode at light load for maximum efficiency across the widest possible range of load currents. The TPS650231 also integrates two general-purpose, 200-mA LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage range from 1.5 V to 6.5 V, thus allowing them to be supplied from one of the step-down converters or directly from the battery. The default output voltage of the LDOs can be digitally set to 4 different voltage combinations using the DEFLDO1 and DEFLDO2 pins. The serial interface can be used for dynamic voltage scaling, masking interrupts, or for disabling, enabling, and setting the LDO output voltages. The interface is compatible with the fast and standard mode I2C specifications, allowing transfers at up to 400 kHz. The TPS650231 is available in a 40-pin VQFN (RSB) package or in a 49-ball DSBGA (YFF) package, and operates over a free-air temperature of –40°C to +85°C.

6 Pin Configuration and Functions

RSB Package
40-Pin VQFN
Top View
TPS650231 pin_out_lvs613.gif

Pin Functions: TPS650231RSB

PIN I/O DESCRIPTION
NAME NO.
SWITCHING REGULATOR SECTION
AGND1 40 — Analog ground. All analog ground pins are connected internally on the chip.
AGND2 17 — Analog ground. All analog ground pins are connected internally on the chip.
DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DEFDCDC1 10 I Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V; DEFDCDC1 can also be connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V.
DEFDCDC2 32 I Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC2 can also be connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V.
DEFDCDC3 1 I Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC3 can also be connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V.
L1 7 — Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
L2 35 — Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
L3 4 — Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
PGND1 8 — Power ground for VDCDC1 converter
PGND2 34 — Power ground for VDCDC2 converter
PGND3 3 — Power ground for VDCDC3 converter
PowerPAD™ — — Connect the power pad to analog ground.
VCC 37 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. VCC also supplies serial interface block.
VDCDC1 9 I VDCDC1 feedback voltage sense input. Connect directly to VDCDC1
VDCDC2 33 I VDCDC2 feedback voltage sense input. Connect directly to VDCDC2
VDCDC3 2 I VDCDC3 feedback voltage sense input. Connect directly to VDCDC3
VINDCDC1 6 I Input voltage for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage supply as VINDCDC2, VINDCDC3, and VCC.
VINDCDC2 36 I Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage supply as VINDCDC1, VINDCDC3, and VCC.
VINDCDC3 5 I Input voltage for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage supply as VINDCDC1, VINDCDC2, and VCC.
LDO REGULATOR SECTION
DEFLD01 12 I Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.
DEFLD02 13 I Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.
LDO_EN 22 I Enable input for LDO1 and LDO2. A logic high enables the LDOs, a logic low disables the LDOs.
VBACKUP 15 I Connect the backup battery to this input pin
VINLDO 19 I Input voltage for LDO1 and LDO2
VLDO1 20 O Output voltage of LDO1
VLDO2 18 O Output voltage of LDO2
VRTC 16 O Output voltage of the LDO and switch for the real-time clock
VSYSIN 14 I Input of system voltage for VRTC switch
CONTROL AND I2C SECTION
HOT_RESET 11 I Push button input that reboots or wakes up the processor through RESPWRON output pin.
INT 28 O Open drain output
LOW_BAT 21 O Open drain output of LOW_BAT comparator
LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output
PWRFAIL 31 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output
RESPWRON 27 O Open drain system reset output
SCLK 30 I Serial interface clock line
SDAT 29 I/O Serial interface data and address
TRESPWRON 26 I Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms
YFF Package
49-Pin DSBGA
Bottom View
TPS650231 po1_lvsae3.gif

Pin Functions: TPS650231YFF

PIN I/O DESCRIPTION
NAME NO.
SWITCHING REGULATOR SECTION
AGND B1, E6 Analog ground. All analog ground pins are connected internally on the chip.
DCDC1_EN F5 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN F6 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN G5 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DEFDCDC1 D5 I Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V; DEFDCDC1 can also be connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1 converter is set in a range from 0.6 V to VINDCDC1 V.
DEFDCDC2 G3 I This pin needs to be connected to a resistor divider between VDCDC2 and GND. The output voltage of the DCDC2 converter is set in a range from 0.6 V to VINDCDC2 V.
DEFDCDC3 C1 I Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V; DEFDCDC3 can also be connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3 converter is set in a range from 0.6 V to VINDCDC3 V.
L1 A5, B5, C5 O Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.
L2 E1, E2, E3 O Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.
L3 A2, B3 O Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.
PGND1 A6, B6, C6 Power ground for VDCDC1 converter
PGND2 F1, F2, F3 Power ground for VDCDC2 converter
PGND3 A1, B2 Power ground for VDCDC3 converter
VCC D4 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 DC-DC converters. VCC must be connected to the same voltage supply as VINDCDC13 and VINDCDC2. VCC also supplies the serial interface block.
VDCDC1 A7 I VDCDC1 feedback voltage sense input. Connect directly to VDCDC1
VDCDC2 E4 I VDCDC2 feedback voltage sense input. Connect directly to VDCDC2
VDCDC3 C3 I VDCDC3 feedback voltage sense input. Connect directly to VDCDC3
VINDCDC13 A3, A4,
B4, C4		 I Input voltage for VDCDC1 and VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC2 and VCC.
VINDCDC2 D1, D2, D3 I Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage supply as VINDCDC13 and VCC.
LDO REGULATOR SECTION
DEFLD01 B7 I Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.
DEFLD02 C7 I Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.
LDO_EN G6 I Enable input for LDO1 and LDO2. A logic high enables the LDOs, a logic low disables the LDOs.
VBACKUP D7 I Connect the backup battery to this input pin
VINLDO F7 I Input voltage for LDO1 and LDO2
VLDO1 G7 O Output voltage of LDO1
VLDO2 E7 O Output voltage of LDO2
VRTC E5 O Output voltage of the LDO and switch for the real-time clock
VSYSIN D6 I Input of system voltage for VRTC switch
CONTROL AND I2C SECTION
PWRFAIL G1 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
PWRFAIL_SNS C2 I Input for the comparator driving the PWRFAIL output
SCLK G2 I Serial interface clock line
SDAT F4 I/O Serial interface data and address
TRESPWRON G4 I Connect a 1-nF capacitor from this pin to GND

 
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