SLVSB16E November   2011  – December 2015 TPS43340-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Inputs
      2. 7.3.2 Linear Regulator (LREG1)
      3. 7.3.3 Gate-Driver Supply (VREG, EXTSUP)
      4. 7.3.4 External P-Channel Drive (GPULL) and Reverse Battery Protection
      5. 7.3.5 Undervoltage Lockout and Overvoltage Protection
      6. 7.3.6 Synchronous Buck Converter Buck3
        1. 7.3.6.1 Soft Start and Foldback Functions
        2. 7.3.6.2 Current-Mode Control and Current-Limit Protection
        3. 7.3.6.3 Operation in Dropout and Undervoltage Protection
        4. 7.3.6.4 Slew Rate Control (SLEW)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.4.1.1 Setting the Operating Frequency
        2. 7.4.1.2 Feedback Inputs
        3. 7.4.1.3 Soft-Start Inputs
        4. 7.4.1.4 Current-Mode Operation
        5. 7.4.1.5 Current Sensing and Current Limit With Foldback
        6. 7.4.1.6 Slope Compensation
        7. 7.4.1.7 Reset Outputs and Filter Delays
        8. 7.4.1.8 Light-Load PFM Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 High- and Low-Side Power NMOS Selection for the Buck Converters
        2. 8.2.2.2 Buck1 Component Selection
        3. 8.2.2.3 Buck2 Component Selection
        4. 8.2.2.4 Buck3 Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
      1. 10.3.1 Power Dissipation of Buck1 and Buck2 (VOUT1 and VOUT2)
      2. 10.3.2 Power Dissipation of Buck Converter Buck3 (VOUT3)
        1. 10.3.2.1 High-Side Switch
        2. 10.3.2.2 Low-Side Switch
        3. 10.3.2.3 Linear Regulator (LREG1)
        4. 10.3.2.4 IC Power Consumption
    4. 10.4 Thermal Considerations
      1. 10.4.1 Phase Configuration
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

PHP Package
48-Pin HTQFP With Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BOOT1 48 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck converter Buck1. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
BOOT2 37 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck converter Buck2. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
BOOT3 14 I A capacitor between BOOT3 and PH3 acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck converter Buck3. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
COMP1 8 O Error amplifier output of Buck1 and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the respective inductor. Clamping this voltage on the upper and lower ends provides current-limit protection for the external MOSFETs.
COMP2 29 O Error amplifier output of Buck2 and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the respective inductor. Clamping this voltage on the upper and lower ends provides current-limit protection for the external MOSFETs.
COMP3 18 O Error amplifier output of Buck3 and compensation node for voltage loop stability. The voltage at this node sets the target for the peak current through the respective inductor.
EN1 22 I Enable input for Buck1. This input has an internal pullup with approximately 0.5 µA of current.
EN2 21 I Enable input for Buck2. This input has an internal pullup with approximately 0.5 µA of current.
EN3 20 I Enable input for Buck3. This input has an internal pullup with approximately 0.5 µA of current.
EN4 47 I Enable input for LREG1 (active-high with an internal pullup current source). An input voltage higher than VIH enables the regulator, whereas an input voltage lower than VIL disables the regulator. This input has an internal pullup with approximately 0.5 µA of current.
EXTSUP 40 I One can use EXTSUP to supply the VREG regulator from one of theTPS43340 buck regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. When EXTSUP is open or lower than 4.6 V, VIN powers the regulator. If EXTSUP is unused, leave the pin open without a capacitor installed.
GL1 3 O External low-side N-channel MOSFET gate drive for buck regulator Buck1. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GL2 34 O External low-side N-channel MOSFET for buck regulator This output can drive Buck2. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GND 26 O Analog ground reference
GPULL 39 O Gate-driver output to implement the reverse-battery protection by an external PMOS. See the Application Information section for more details.
GU1 1 O External high-side N-channel MOSFET gate drive for buck regulator Buck1. The output provides high peak currents to drive capacitive loads. The gate-drive reference is a floating-ground reference provided by PH1 and has a voltage swing provided by BOOT1.
GU2 36 O This output can drive an external high-side N-channel MOSFET for buck regulator Buck2. The output provides high peak currents to drive capacitive loads. The gate-drive reference is a floating-ground reference provided by PH2 and has a voltage swing provided by BOOT2.
LREG1 46 O Linear regulator output. Decouple with a low-ESR ceramic output capacitor in the range of 1 µF to 47 µF connected from this terminal to ground.
PGND1 4 O Power ground connection for the GL1 driver. Connect to the source of the low-side N-channel MOSFET of Buck1.
PGND2 33 O Power ground connection to the source of the low-side N-channel MOSFETs of Buck2
PGND3 12 O Buck3 power ground
PH1 2 O Switching terminal of buck regulator Buck1, providing a floating ground reference for the high-side MOSFET gate-driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desirable.
PH2 35 O Switching terminal of buck regulator Buck2, providing a floating ground reference for the high-side MOSFET gate-driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desirable.
PH3 13 O Switching terminal of buck converter Buck3. Also provides a floating ground reference for the high-side MOSFET gate-driver circuitry
Rdelay 24 O The capacitor at the Rdelay pin sets the power-good delay interval used to de-glitch the outputs of the power-good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 μs, typical.
RST1 9 O Open-drain power-good output for Buck1, with a 50-kΩ pullup resistor to S2. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls by RSTxth1 of the set value.
RST2 28 O Open-drain power-good output for Buck2 with a 50 kΩ pullup resistor to S4. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls by RSTxth1 of the set value.
RST3 16 O Open-drain power-good output for Buck3. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls by RSTxth1 of the set value.
RST4 44 O Open-drain power-good indicator pin for LREG1, with a 50-kΩ pullup resistor to LREG1. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls by RSTxth1 of the set value.
RT 25 O Connecting a resistor to analog ground on this pin sets the operating switching frequency of the buck controllers and converter. Shorting this pin to ground or leaving it open defaults operation to 400 kHz for the buck controllers and the converter.
S1 6 I High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for the buck controller. For details, see the Functional Description section.
S2 5 I
S3 31 I
S4 32 I
SLEW 19 I Slew rate (dV/dt) selector of the internal high-side switching MOSFET for Buck3. For details, see the Application Information section.
SS1 10 O Soft-start or tracking input for buck controller Buck1. The buck controller regulates the VSENSE1 voltage to the lower of 0.8 V or the SS1 pin voltage. An internal pullup current source of 1 μA is present at the pin, and use of an appropriate capacitor connected here can set the soft-start ramp duration. Alternatively, use of a resistor divider from another supply can provide a tracking input to this pin.
SS2 27 O Soft-start or tracking input for buck controller Buck2. The buck controller regulates the VSENSE2 voltage to the lower of 0.8 V or the SS2 pin voltage. An internal pullup current source of 1 μA is present at the pin, and use of an appropriate capacitor connected here can set the soft-start ramp interval. Alternatively, use of a resistor divider from another supply can provide a tracking input to this pin.
SS3 15 O Soft-start or tracking input for buck converter Buck3. The buck converter regulates the VSENSE3 voltage to the lower of 0.8 V or the SS3 pin voltage. An internal pullup current source of 1 μA is present at the pin, and an appropriate capacitor connected here can set the soft-start ramp duration. Alternatively, use of a resistor divider from another supply can provide a tracking input to this pin.
SYNC 23 I PLL synchronization, low-power mode-control pin. If an external clock is present on this pin, the device detects it and the internal PLL locks on to the external clock. This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. For details, see the Application Information section.
VIN 41 I Main Input pin. This is the buck controller and buck converter input pin. Additionally, it powers the internal control circuits of the device. Connect a bypass capacitor to filter noise between this pin and signal ground.
VIN2SENSE 43 I Supply-voltage sense input for the current mode of Buck2. Connect to the drain of the high-side-FET of Buck2. Cascading Buck1 as the supply for the Buck2 configuration does not support LPM on Buck2.
VLR1 42 I The VLR1 terminal is the input voltage source for the linear regulator supply. This pin requires an input capacitor to ground to filter any noise present on the line.
VREG 38 O This pin requires an external capacitor to provide a regulated supply for the gate drivers of the buck controllers and converter. The regulator can obtain power either from VIN or EXTSUP. This pin has current limit-protection; do not use it to drive any other loads.
VSENSE1 7 I Feedback voltage pin for Buck1. For details, see the Application Information section.
VSENSE2 30 I Feedback voltage pin for Buck2. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage.
VSENSE3 17 I Feedback voltage pin for Buck3. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage.
VSENSE4 45 I Feedback voltage pin for linear regulator LREG1. LREG1 regulates the feedback voltage to the internal reference. A suitable resistor divider network between the LDO output and the feedback pin sets the desired output voltage. See the LREG1 parameters and the Application Information section.
VSUP 11 I Power supply for the Buck3 regulator. Provide good decoupling to PGND3 with a ceramic capacitor close to the pins.