The DRV8834 provides a flexible motor driver solution for toys, printers, cameras, and other mechatronic applications. The device has two H-bridge drivers, and is intended to drive a bipolar stepper motor or two DC motors.
The output driver block of each H-bridge consists of N-channel power MOSFETs configured as an H-bridge to drive the motor windings. Each H-bridge includes circuitry to regulate or limit the winding current.
With proper PCB design, each H-bridge of the DRV8834 can driving up to 1.5-A RMS (or DC) continuously, at 25°C with a VM supply of 5 V. The device can support peak currents of up to 2.2 A per bridge. Current capability is reduced slightly at lower VM voltages.
Internal shutdown functions with a fault output pin are provided for overcurrent protection, short-circuit protection, undervoltage lockout and overtemperature. A low-power sleep mode is also provided.
The DRV8834 is packaged in a 24-pin HTSSOP or VQFN package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8834 | HTSSOP (24) | 7.80 mm × 4.40 mm |
VQFN (24) | 4.00 mm × 4.00 mm |
Changes from C Revision (June 2013) to D Revision
PIN | I/O | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS |
||
---|---|---|---|---|---|
NAME | HTSSOP | VQFN | |||
POWER AND GROUND | |||||
GND | 21, PPAD |
18, PPAD |
— | Device ground | Both the GND pin and device PowerPAD must be connected to ground |
VM | 18, 19 | 15, 16 | — | Bridge A power supply | Connect to motor supply. A 10-µF (minimum) capacitor to GND is recommended. |
VINT | 20 | 17 | — | Internal supply | Bypass to GND with 2.2-μF (minimum), 6.3-V capacitor. Can be used to provide logic high voltage for configuration pins (except nSLEEP). |
VREFO | 24 | 21 | O | Reference voltage output | May be connected to AVREF/BVREF inputs. Do not place a bypass capacitor on this pin. |
VCP | 17 | 14 | O | High-side gate drive voltage | Connect a 0.01-μF, 16-V (minimum) X7R ceramic capacitor to VM. |
CONTROL (INDEXER MODE OR PHASE/ENABLE MODE) | |||||
nENBL/AENBL | 10 | 7 | I | Step motor enable/Bridge A enable | Indexer mode: Logic low enables all outputs. Phase/enable mode: Logic high enables the AOUTx outputs. Internal pulldown. |
STEP/BENBL | 11 | 8 | I | Step input/Bridge B enable | Indexer mode: Rising edge moves indexer to next step. Phase/enable mode: Logic high enables the BOUTx outputs. Internal pulldown. |
DIR/BPHASE | 12 | 9 | I | Direction input/Bridge B Phase | Indexer mode: Level sets direction of step. Phase/enable mode: Logic high sets BOUT1 high, BOUT2 low. Internal pulldown. |
M0/APHASE | 13 | 10 | I | Microstep mode/Bridge A phase | Indexer mode: Controls microstep mode (full, half, up to 1/32-step) along with M1. Phase/enable mode: Logic high sets AOUT1 high, AOUT2 low. Internal pulldown. |
M1 | 14 | 11 | I | Microstep mode/Disable state | Indexer mode: Controls microstep mode (full, half, up to 1/32-step) along with M0. Phase/enable mode: Determines the state of the outputs when xENBL = 0. Internal pulldown. |
CONFIG | 15 | 12 | I | Device configuration | Logic high to put the device in indexer mode. Logic low to put the device into phase/enable mode. State is latched at power up and sleep exit. Internal pulldown. |
nSLEEP | 1 | 22 | I | Sleep mode input | Logic high to enable device, logic low to enter low-power sleep mode and reset all internal logic. |
AVREF | 22 | 19 | I | Bridge A current set reference input | Reference voltage for AOUT winding current. In Indexer Mode, it should be tied to a reference voltage for the internal DAC (for example, VREFO). In Phase/Enable Mode, an external DAC can drive it for microstepping. |
BVREF | 23 | 20 | I | Bridge B current set reference input | Reference voltage for BOUT winding current. In Indexer Mode, it should be tied to a reference voltage for the internal DAC (for example, VREFO). In Phase/Enable Mode, an external DAC can drive it for microstepping. |
ADECAY | 3 | 24 | I | Decay mode for bridge A | Determines decay mode for H-Bridge A (or A and B in indexer mode) – slow, fast or mixed decay |
BDECAY | 2 | 23 | I | Decay mode for bridge B | Determines decay mode for H-Bridge B – slow, fast or mixed decay |
STATUS | |||||
nFAULT | 16 | 13 | OD | Fault output | Logic low when in fault condition (overtemp, overcurrent, undervoltage) |
OUTPUT | |||||
AISEN | 5 | 2 | IO | Bridge A ground/Isense | Connect to current sense resistor for bridge A, or GND if current control not needed |
BISEN | 8 | 5 | IO | Bridge B ground/Isense | Connect to current sense resistor for bridge B, or GND if current control not needed |
AOUT1 | 4 | 1 | O | Bridge A output 1 | Connect to motor winding A |
AOUT2 | 6 | 3 | O | Bridge A output 2 | |
BOUT1 | 9 | 6 | O | Bridge B output 1 | Connect to motor winding B |
BOUT2 | 7 | 4 | O | Bridge B output 2 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VM | Power supply voltage | –0.3 | 11.8 | V | |
AVREF, BVREF, VINT, ADECAY, BDECAY |
Analog input pin voltage | –0.5 | 3.6 | V | |
Digital input pin voltage | –0.5 | 7 | V | ||
xISEN pin voltage | –0.3 | 0.5 | V | ||
Peak motor drive output current, t < 1 µs | Internally limited | A | |||
TJ | Operating virtual junction temperature | –40 | 150 | °C | |
Tstg | Storage temperature | –60 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±4000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VM | Motor power supply voltage range(1) | 2.5 | 10.8 | V | |
VREF | VREF input voltage range(2) | 1 | 2.1 | V | |
IVINT | VINT external load current | 1 | mA | ||
IVREF | VREF external load current | 400 | µA | ||
VDIGIN | Digital input pin voltage range | –0.3 | 5.75 | V | |
IOUT | Continuous RMS or DC output current per bridge(3) | 1.5 | A |
THERMAL METRIC(1) | DRV8834 | UNIT | ||
---|---|---|---|---|
PWP [HTSSOP] | RGE [VQFN] | |||
24 PINS | 24 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 40.2 | 35.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 23.7 | 36.6 | |
RθJB | Junction-to-board thermal resistance | 21.9 | 12.2 | |
ψJT | Junction-to-top characterization parameter | 0.7 | 0.6 | |
ψJB | Junction-to-board characterization parameter | 21.7 | 12.2 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.9 | 4 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
IVM | VM operating supply current | VM = 5 V, excluding winding current | 2.4 | 4 | mA | |
VM = 10 V, excluding winding current | 2.75 | |||||
IVMQ | VM sleep mode supply current | VM = 5 V | 0.6 | 2 | μA | |
VM = 10 V | 9.6 | |||||
VUVLO | VM undervoltage lockout voltage | VM falling | 2.39 | V | ||
INTERNAL REGULATORS | ||||||
VINT | VINT voltage | VM > 3.3 V, IOUT = 0 A to 1 mA | 2.85 | 3 | 3.15 | V |
VREFO | VREF voltage | IOUT = 0 A to 400 µA | 1.9 | 2 | 2.1 | V |
LOGIC-LEVEL INPUTS | ||||||
VIL | Input low voltage | nSLEEP | 0.5 | V | ||
All other digital input pins | 0.7 | |||||
VIH | Input high voltage | nSLEEP | 2.5 | V | ||
All other digital input pins | 2 | |||||
VHYS | Input hysteresis | nSLEEP | 0.2 | V | ||
All except nSLEEP | 0.4 | |||||
RPD | Input pulldown resistance | nSLEEP | 500 | kΩ | ||
All except nSLEEP, M0 | 200 | |||||
IIL | Input low current | VIN = 0 | 1 | μA | ||
IIN | Input current (M0) | -20 | 20 | µA | ||
IIH | Input high current | VIN = 3.3 V, nSLEEP | 6.6 | 13 | μA | |
VIN = 3.3 V, all except nSLEEP | 16.5 | 33 | ||||
tDEG | Input deglitch time | 312 | 468 | ns | ||
nFAULT OUTPUT (OPEN-DRAIN OUTPUT) | ||||||
VOL | Output low voltage | IO = 5 mA | 0.5 | V | ||
IOH | Output high leakage current | VO = 3.3 V | 1 | μA | ||
H-BRIDGE FETs | ||||||
RDS(ON) | HS FET ON-resistance | VM = 5 V, IO = 500 mA, TJ = 25°C | 160 | 250 | mΩ | |
VM = 5 V, IO = 500 mA, TJ = 85°C | 190 | |||||
VM = 2.7 V, IO = 500 mA, TJ = 25°C | 200 | 295 | ||||
VM = 2.7 V, IO = 500 mA, TJ = 85°C | 240 | |||||
LS FET ON-resistance | VM = 5 V, IO = 500 mA, TJ = 25°C | 145 | 240 | |||
VM = 5 V, IO = 500 mA, TJ = 85°C | 180 | |||||
VM = 2.7 V, IO = 500 mA, TJ = 25°C | 190 | 285 | ||||
VM = 2.7 V, IO = 500 mA, TJ = 85°C | 235 | |||||
IOFF | Off-state leakage current | –2 | 2 | μA | ||
MOTOR DRIVER | ||||||
fPWM | Current control PWM frequency | Internal PWM frequency | 42.5 | kHz | ||
tBLANK | Current sense blanking time | VREF > 375 mV or DAC codes > 29% | 2.4 | µs | ||
VREF < 375 mV or DAC codes < 29% | 1.6 | |||||
tR | Rise time | VM = 5 V, 16 Ω to GND, 10% to 90% VM | 120 | ns | ||
tF | Fall time | VM = 5 V, 16 Ω to GND, 10% to 90% VM | 100 | ns | ||
PROTECTION CIRCUITS | ||||||
IOCP | Overcurrent protection trip level | 2 | A | |||
tOCP | Overcurrent protection period | VREF > 375 mV or DAC codes > 29% | 1.6 | µs | ||
VREF < 375 mV or DAC codes < 29% | 1.1 | |||||
tTSD | Thermal shutdown temperature | Die temperature | 150 | 160 | 180 | °C |
CURRENT CONTROL | ||||||
IREF | VREF input current | VREF = 3.3 V | –1 | 1 | µA | |
VTRIP | xISEN trip voltage | For 100% current step | xVREF/5 | V | ||
AISENSE | Current sense amplifier gain | Reference only | 5 | V/V |
NO. | PARAMETER | CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
1 | fSTEP | Step frequency | 250 | kHz | ||
2 | tWH(STEP) | Pulse duration, STEP high | 1.9 | µs | ||
3 | tWL(STEP) | Pulse duration, STEP low | 1.9 | µs | ||
4 | tSU(STEP) | Setup time, command to STEP rising | 200 | ns | ||
5 | tH(STEP) | Hold time, command to STEP rising | 1 | µs | ||
6 | tWAKE | Wake-up time, nSLEEP inactive to STEP | 1 | ms |
The DRV8834 supports two configurations: phase/enable mode, where the outputs are controlled by phase (direction) and enable signals for each H-bridge, and indexer mode, which allow control of a stepper motor using simple step and direction inputs.
DC motors can only be controlled in phase/enable mode; indexer mode is not applicable to DC motors.
Stepper motors can be controlled using either phase/enable load, or indexer mode.
The device is configured to be controlled either way using CONFIG pin. Logic HIGH on the CONFIG pin puts the device in the STEP/DIR mode; logic LOW lets the motor to be controlled using the xPHASE/xENBL pins.
The state of the CONFIG pin is latched at power up, and also whenever exiting sleep mode. CONFIG has an internal pulldown resistor.
DRV8834 contains two identical H-bridge motor drivers with current-control PWM circuitry. A block diagram of the circuitry is shown in Figure 6:
The current through the motor windings may be regulated by a fixed-frequency PWM current regulation (current chopping).
With stepping motors, current control is normally used at all times. Often it is used to vary the current in the two windings in a sinusoidal fashion to provide smooth motion. This is referred to as microstepping. The DRV8834 can provide up to 1/32 step microstepping, using internal 5-bit DACs. Finer microstepping can be implemented using the xPHASE/xENBL signals to control the stepper motor, and varying the xVREF voltages. The current flowing through the corresponding H-bridge varies according to the equation given below. A very high degree of microstepping can be achieved through this technique.
With DC motors, current control can be used to limit the start-up current of the motor to less than the stall current of the motor.
Current regulation works as follows:
When an H-bridge is enabled, current rises through the winding at a rate dependent on the supply voltage and inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle. Immediately after the current is enabled, the voltage on the xISEN pin is ignored for a period of time before enabling the current sense circuitry. This blanking time also sets the minimum on time of the PWM when operating in current chopping mode.
The blanking time also sets the minimum PWM duty cycle. This can cause current control errors near the zero current level when microstepping. To help eliminate this error, the DRV8834 has a dynamic tBLANK time. When the commanded current is low, the blanking period is reduced, which in turn lowers the minimum duty cycle. This provides a smoother current transition across the zero crossing region of the current waveform. The end result is smoother and quieter motor operation.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, with a reference voltage supplied to the AVREF and BVREF pins. In indexer mode, the reference voltages are scaled by internal DACs to provide scaled currents used to perform microstepping.
The chopping current is calculated as follows:
Example: If xVREF is 2 V (as it would be if xVREF is connected directly to VREFO) and a 400-mΩ sense resistor is used, the chopping current will be 2 V / 5 × 400 mΩ = 1 A.
In indexer mode, this current value is scaled by between 5% and 100% by the internal DACs, as shown in the step table in the "Microstepping Indexer" section of the data sheet.
If current control is not needed, the xISEN pins may be connected directly to ground. In this case, TI also recommends connecting AVREF and BVREF directly to VREFO.
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 7 as case 1. The current flow direction shown indicates positive current flow in the step table below for indexer mode, or the current flow with xPHASE = 1 in phase/enable mode.
Once the chopping current threshold is reached, the drive current is interrupted, but due to the inductive nature of the motor, the current must continue to flow. This is called recirculation current. To handle this recirculation current, the H-bridge can operate in two different states, fast decay or slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in through the opposing FETs. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 7 as case 2.
In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. Slow decay is shown as case 3 in Figure 7.
The DRV8834 supports fast, slow, and also mixed decay modes. With DC motors, slow decay is nearly always used to minimize current ripple and optimize speed control; with stepper motors, the decay mode is chosen for a given stepper motor and operating conditions to minimize mechanical noise and vibration.
In mixed decay mode, the current recirculation begins as fast decay, but at a fixed period of time (determined by the state of the xDECAY pins shown in Table 1) switches to slow decay mode for the remainder of the fixed PWM period.
RESISTANCE ON xDECAY PIN | -OR- VOLTAGE FORCED ON xDECAY PIN | % OF PWM CYCLE IS FAST DECAY |
---|---|---|
< 1 kΩ | < 0.1 V | 0% |
20 kΩ ±5% | 0.2 V ±5% | 25% |
50 kΩ ±5% | 0.5 V ±5% | 50% |
100 kΩ ±5% | 1 V ±5% | 75% |
> 200 kΩ | > 2 V | 100% |
Figure 8 shows the current waveforms in slow, 25% mixed, and fast decay modes.
Decay mode is selected by the voltage present on the xDECAY pins. Internal current sources of 10 µA (typical) are connected to the pins, which allows setting of the decay mode by a resistor connected to ground if desired.
It is possible to drive the xDECAY pin with a tristate GPIO pin and also place the resistor to ground. This allows a microcontroller to select fast, slow, or mixed decay modes by driving the pin high, low, or high-impedance. The logic-low voltage must be less than 0.1 V with 10-µA of current sourced from the DRV8834 to attain slow decay.
In indexer mode, only the ADECAY pin is used, and slow decay mode is always used when at any point in the step table where the current is increasing. When current is decreasing or remaining constant, the decay mode used will be fast, slow, or mixed, as commanded by the ADECAY pin.
The DRV8834 is fully protected against undervoltage, overcurrent and overtemperature events.
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge are disabled and the nFAULT pin are driven low. The driver will be re-enabled after the OCP retry period (approximately 1.2 ms) has passed. nFAULT becomes high again at this time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and nFAULT remains deasserted. Only the H-bridge in which the OCP is detected will be disabled while the other bridge will function normally.
Overcurrent conditions are detected independently on both high-side and low-side devices; that is, a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for PWM current control, so functions even without presence of the xISEN resistors.
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. When the die temperature falls to a safe level, operation automatically resumes and nFAULT becomes inactive.
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and all internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. The nFAULT pin is driven low during an undervoltage condition, and also at power up or sleep mode, until the internal power supplies have stabilized.
In phase/enable mode, the xPHASE input pins control the direction of current flow through each H-bridge. This sets the direction of rotation of a DC motor, or the direction of the current flow in a stepper motor winding. Driving the xENBL input pins active high enables the H-bridge outputs. This can be used as PWM speed control of a DC motor, or to enable/disable the current in a stepper motor.
In phase/enable mode, the M1 input pin controls the state of the H-bridges when xENBL = 0. If M1 is high, the outputs are disabled (high impedance) when xENBL = 0; this corresponds to asynchronous fast decay mode, and is usually used in stepper motor applications to command a "zero current" state. If M1 is low, then the outputs are both driven low; this corresponds to slow decay or brake mode, and is usually used when controlling the speed of a DC motor by PWMing the xENBL pin.
M1 | xENBL | xPHASE | xOUT1 | xOUT2 |
---|---|---|---|---|
1 | 0 | X | Z | Z |
0 | 0 | X | 0 | 0 |
X | 1 | 0 | L | H |
X | 1 | 1 | H | L |
To allow a simple step and direction interface to control stepper motors, the DRV8834 contains a microstepping indexer. The indexer controls the state of the H-bridges automatically. Whenever there is a rising edge at the STEP input, the indexer moves to the next step, according to the direction set by the DIR pin.
The nENBL pin is used to disable the output stage in indexer mode. When nENBL = 1, the indexer inputs are still active and will respond to the STEP and DIR input pins; only the output stage is disabled.
The indexer logic in the DRV8834 allows a number of different stepping configurations. The M0 and M1 pins are used to configure the stepping format as shown in Table 3.
M1 | M0 | STEP MODE |
---|---|---|
0 | 0 | Full step (2-phase excitation) |
0 | 1 | 1/2 step (1-2 phase excitation) |
0 | Z | 1/4 step (W1-2 phase excitation) |
1 | 0 | 8 microsteps/step |
1 | 1 | 16 microsteps/step |
1 | Z | 32 microsteps/step |
The M0 pin is a tri-level input. It can be driven logic low, logic high, or high-impedance (Z).
The M0 and M1 pins can be statically configured by connecting to VINT, GND, or left open, or can be driven with standard tristate microcontroller I/O port pins. Their state is latched at each rising edge of the STEP input.
The step mode may be changed on-the-fly while the motor is moving. The indexer will advance to the next valid state for the new M0/M1 setting at the next rising edge of STEP.
The home state is 45°. This state is entered after power up, after exiting undervoltage lockout, or after exiting sleep mode. This is shown in Table 4 by cells shaded yellow.
Table 4 shows the relative current and step directions for different step mode settings. At each rising edge of the STEP input, the indexer travels to the next state in the table. The direction is shown with the DIR pin high; if the DIR pin is low the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to xOUT2.
1/32 STEP | 1/16 STEP | 1/8 STEP | 1/4 STEP | 1/2 STEP | FULL STEP 70% | WINDING CURRENT A | WINDING CURRENT B | ELECTRICAL ANGLE |
---|---|---|---|---|---|---|---|---|
1 | 1 | 1 | 1 | 1 | 100% | 0% | 0 | |
2 | 100% | 5% | 3 | |||||
3 | 2 | 100% | 10% | 6 | ||||
4 | 99% | 15% | 8 | |||||
5 | 3 | 2 | 98% | 20% | 11 | |||
6 | 97% | 24% | 14 | |||||
7 | 4 | 96% | 29% | 17 | ||||
8 | 94% | 34% | 20 | |||||
9 | 5 | 3 | 2 | 92% | 38% | 23 | ||
10 | 90% | 43% | 25 | |||||
11 | 6 | 88% | 47% | 28 | ||||
12 | 86% | 51% | 31 | |||||
13 | 7 | 4 | 83% | 56% | 34 | |||
14 | 80% | 60% | 37 | |||||
15 | 8 | 77% | 63% | 39 | ||||
16 | 74% | 67% | 42 | |||||
17 | 9 | 5 | 3 | 2 | 1 | 71% | 71% | 45 |
18 | 67% | 74% | 48 | |||||
19 | 10 | 63% | 77% | 51 | ||||
20 | 60% | 80% | 53 | |||||
21 | 11 | 6 | 56% | 83% | 56 | |||
22 | 51% | 86% | 59 | |||||
23 | 12 | 47% | 88% | 62 | ||||
24 | 43% | 90% | 65 | |||||
25 | 13 | 7 | 4 | 38% | 92% | 68 | ||
26 | 34% | 94% | 70 | |||||
27 | 14 | 29% | 96% | 73 | ||||
28 | 24% | 97% | 76 | |||||
29 | 15 | 8 | 20% | 98% | 79 | |||
30 | 15% | 99% | 82 | |||||
31 | 16 | 10% | 100% | 84 | ||||
32 | 5% | 100% | 87 | |||||
33 | 17 | 9 | 5 | 3 | 0% | 100% | 90 | |
34 | –5% | 100% | 93 | |||||
35 | 18 | –10% | 100% | 96 | ||||
36 | –15% | 99% | 98 | |||||
37 | 19 | 10 | –20% | 98% | 101 | |||
38 | –24% | 97% | 104 | |||||
39 | 20 | –29% | 96% | 107 | ||||
40 | –34% | 94% | 110 | |||||
41 | 21 | 11 | 6 | –38% | 92% | 113 | ||
42 | –43% | 90% | 115 | |||||
43 | 22 | –47% | 88% | 118 | ||||
44 | –51% | 86% | 121 | |||||
45 | 23 | 12 | –56% | 83% | 124 | |||
46 | –60% | 80% | 127 | |||||
47 | 24 | –63% | 77% | 129 | ||||
48 | –67% | 74% | 132 | |||||
49 | 25 | 13 | 7 | 4 | 2 | –71% | 71% | 135 |
50 | –74% | 67% | 138 | |||||
51 | 26 | –77% | 63% | 141 | ||||
52 | –80% | 60% | 143 | |||||
53 | 27 | 14 | –83% | 56% | 146 | |||
54 | –86% | 51% | 149 | |||||
55 | 28 | –88% | 47% | 152 | ||||
56 | –90% | 43% | 155 | |||||
57 | 29 | 15 | 8 | –92% | 38% | 158 | ||
58 | –94% | 34% | 160 | |||||
59 | 30 | –96% | 29% | 163 | ||||
60 | –97% | 24% | 166 | |||||
61 | 31 | 16 | –98% | 20% | 169 | |||
62 | –99% | 15% | 172 | |||||
63 | 32 | –100% | 10% | 174 | ||||
64 | –100% | 5% | 177 | |||||
65 | 33 | 17 | 9 | 5 | –100% | 0% | 180 | |
66 | –100% | –5% | 183 | |||||
67 | 34 | –100% | –10% | 186 | ||||
68 | –99% | –15% | 188 | |||||
69 | 35 | 18 | –98% | –20% | 191 | |||
70 | –97% | –24% | 194 | |||||
71 | 36 | –96% | –29% | 197 | ||||
72 | –94% | –34% | 200 | |||||
73 | 37 | 19 | 10 | –92% | –38% | 203 | ||
74 | –90% | –43% | 205 | |||||
75 | 38 | –88% | –47% | 208 | ||||
76 | –86% | –51% | 211 | |||||
77 | 39 | 20 | –83% | –56% | 214 | |||
78 | –80% | –60% | 217 | |||||
79 | 40 | –77% | –63% | 219 | ||||
80 | –74% | –67% | 222 | |||||
81 | 41 | 21 | 11 | 6 | 3 | –71% | –71% | 225 |
82 | –67% | –74% | 228 | |||||
83 | 42 | –63% | –77% | 231 | ||||
84 | –60% | –80% | 233 | |||||
85 | 43 | 22 | –56% | –83% | 236 | |||
86 | –51% | –86% | 239 | |||||
87 | 44 | –47% | –88% | 242 | ||||
88 | –43% | –90% | 245 | |||||
89 | 45 | 23 | 12 | –38% | –92% | 248 | ||
90 | –34% | –94% | 250 | |||||
91 | 46 | –29% | –96% | 253 | ||||
92 | –24% | –97% | 256 | |||||
93 | 47 | 24 | –20% | –98% | 259 | |||
94 | –15% | –99% | 262 | |||||
95 | 48 | –10% | –100% | 264 | ||||
96 | –5% | –100% | 267 | |||||
97 | 49 | 25 | 13 | 7 | 0% | –100% | 270 | |
98 | 5% | –100% | 273 | |||||
99 | 50 | 10% | –100% | 276 | ||||
100 | 15% | –99% | 278 | |||||
101 | 51 | 26 | 20% | –98% | 281 | |||
102 | 24% | –97% | 284 | |||||
103 | 52 | 29% | –96% | 287 | ||||
104 | 34% | –94% | 290 | |||||
105 | 53 | 27 | 14 | 38% | –92% | 293 | ||
106 | 43% | –90% | 295 | |||||
107 | 54 | 47% | –88% | 298 | ||||
108 | 51% | –86% | 301 | |||||
109 | 55 | 28 | 56% | –83% | 304 | |||
110 | 60% | –80% | 307 | |||||
111 | 56 | 63% | –77% | 309 | ||||
112 | 67% | –74% | 312 | |||||
113 | 57 | 29 | 15 | 8 | 4 | 71% | –71% | 315 |
114 | 74% | –67% | 318 | |||||
115 | 58 | 77% | –63% | 321 | ||||
116 | 80% | –60% | 323 | |||||
117 | 59 | 30 | 83% | –56% | 326 | |||
118 | 86% | –51% | 329 | |||||
119 | 60 | 88% | –47% | 332 | ||||
120 | 90% | –43% | 335 | |||||
121 | 61 | 31 | 16 | 92% | –38% | 338 | ||
122 | 94% | –34% | 340 | |||||
123 | 62 | 96% | –29% | 343 | ||||
124 | 97% | –24% | 346 | |||||
125 | 63 | 32 | 98% | –20% | 349 | |||
126 | 99% | –15% | 352 | |||||
127 | 64 | 100% | –10% | 354 | ||||
128 | 100% | –5% | 357 |
Driving nSLEEP low will put the device into a low-power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, all internal logic is reset (this returns the indexer to the home state), the VINT supply is disabled, and all internal clocks are stopped. All inputs are ignored until nSLEEP returns inactive high.
Because the VINT supply is disabled during sleep mode, it cannot be used to provide a logic high signal to the nSLEEP pin. To simplify board design, the nSLEEP can be pulled up directly to the supply (VM) if it is not actively driven. Unless VM is less than 5.75 V, a pullup resistor is required.
The nSLEEP pin is protected by a Zener diode that will clamp the pin voltage to approximately 6.5 V. The pullup resistor limits the current to the input in case VM is higher than 6.5 V. The recommended pullup resistor is 20 kΩ to 50 kΩ.
When exiting sleep mode, the nFAULT pin will be briefly driven active low as the internal power supplies turn on. nFAULT will return to inactive high once the internal power supplies (including charge pump) have stabilized. This process takes some time (up to 1 ms), before the motor driver becomes fully operational.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DRV8834 is a very flexible motor driver. It can be used to drive two DC motors or a stepper motor, in a number of different configurations.
The following applications schematics show various configurations and connections for the DRV8834.
Component values, especially for RSENSE and the DECAY pins, may be different depending on your motor and application. Refer to the information above to determine the best values for these components in your application.
For optimal performance, it is important for the sense resistor to be:
The power dissipated by the sense resistor equals IRMS2 × R. For example, if peak motor current is 3 A, RMS motor current is 2 A, and a 0.05-Ω sense resistor is used, the resistor will dissipate 2A2 × 0.05 Ω = 0.2 W. The power quickly increases with higher current levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve for high ambient temperatures. When a PCB is shared with other components generating heat, margin should be added. It is always best to measure the actual sense resistor temperature in a final system, along with the power MOSFETs, as those are often the hottest components.
Because power resistors are larger and more expensive than standard resistors, it is common practice to use multiple standard resistors in parallel, between the sense node and ground. This distributes the current and heat dissipation.
In this configuration, the DRV8834 is used to drive two independent DC motors. Current up to 1 A per motor is possible. The M1 pin is pulled low to allow slow decay PWM from the controller (if desired) to control the motor speed by PWMing the xENBL inputs, and ADECAY and BDECAY are connected to ground to set slow decay mode during current limiting. The value of the RSENSE resistors shown is for a 1-A current limit; if current limiting is not needed, the AISEN and BISEN pins may be connected directly to ground. If the sleep function is not needed, nSLEEP can be connected to VM with an approximate 47-kΩ resistor.
Table 5 lists the design parameters.
PARAMETER | REFERENCE | EXAMPLE VALUE |
---|---|---|
Motor voltage | VM | 10 V |
Motor RMS current | IRMS | 0.8 A |
Motor start-up current | ISTART | 1 A |
Motor current trip point | ITRIP | 1.5 A |
The motor voltage to use will depend on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings.
The power dissipation of the DRV8834 is a function of RMS motor current and the FET resistance (RDS(ON)) of each output.
For this example, the ambient temperature is 35°C, and the junction temperature reaches 65°C. At 65°C, the sum of RDS(ON) is about 1 Ω. With an example motor current of 0.8 A, the dissipated power in the form of heat will be 0.8 A2 × 1 Ω = 0.64 W.
The temperature that the DRV8834 reaches will depend on the thermal resistance to the air and PCB. It is important to solder the device PowerPAD to the PCB ground plane, with vias to the top and bottom board layers, in order dissipate heat into the PCB and reduce the device temperature. In the example used here, the DRV8834 had an effective thermal resistance RθJA of 47°C/W, and:
When the voltage on pin SENSE exceeds VTRIP (0.5 V), overcurrent is detected. The RSENSE resistor should be sized to set the desired ITRIP level.
To set ITRIP to 2 A, RSENSE = 0.5 V / 2 A = 0.25 Ω.
To prevent false trips, ITRIP must be higher than regular operating current. Motor current during start-up is typically much higher than steady-state spinning, because the initial load torque is higher, and the absence of back-EMF causes a higher voltage and extra current across the motor windings.
It can be beneficial to limit start-up current by using series inductors on the DRV8834 output, as that allows ITRIP to be lower, and it may decrease the system’s required bulk capacitance. Start-up current can also be limited by ramping the forward drive duty cycle.
Table 6 lists the design parameters.
PARAMETER | REFERENCE | EXAMPLE VALUE |
---|---|---|
Supply voltage | VM | 6 V |
Motor winding resistance | RL | 3.9 Ω |
Motor winding inductance | IL | 2.9 mH |
Motor full step angle | θstep | 1.8°/step |
Target microstepping level | nm | 2 µsteps per step |
Target motor speed | V | 120 RPM |
Target full-scale current | IFS | 1.25 A |
Phase/enable mode can be used with a simple interface to a controller to operate a stepper motor in full or half step modes. The decay mode can be set by changing the values of the resistors connected to the ADECAY and BDECAY pins. The M1 pin is driven to logic high (by connecting to the VINT supply), to allow a zero-current (off) state when the xENBL pin is set low. Coil current is set by the RSENSE resistors. If the sleep function is not needed, nSLEEP can be connected to VM with an approximate 47-kΩ resistor.
The first step in configuring the DRV8834 requires the desired motor speed and microstepping level. If the target application requires a constant speed, then a square wave with frequency ƒstep must be applied to the STEP pin.
If the target motor start-up speed is too high, the motor will not spin. Make sure that the motor can support the target speed or implement an acceleration profile to bring the motor up to speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
θstep can be found in the stepper motor data sheet or written on the motor itself.
For the DRV8834, the microstepping level is set by the MODE pins and can be any of the settings in Table 6. Higher microstepping will mean a smoother motor motion and less audible noise, but will increase switching losses and require a higher fstep to achieve the same motor speed.
In a stepper motor, the set full-scale current (IFS) is the maximum current driven through either winding. This quantity will depend on the xVREF analog voltage and the sense resistor value (RSENSE). During stepping, IFS defines the current chopping threshold (ITRIP) for the maximum current step. The gain of DRV8834 is set for 5 V/V.
To achieve IFS = 1.25 A with RSENSE of 0.2 Ω, xVREF should be 1.25 V.
The DRV8834 supports three different decay modes: slow decay, fast decay, and mixed decay. The current through the motor windings is regulated using a fixed-frequency PWM scheme. This means that after any drive phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8834 will place the winding in one of the three decay modes until the PWM cycle has expired. Afterward, a new drive phase starts.
The blanking time TBLANK defines the minimum drive time for the current chopping. ITRIP is ignored during TBLANK, so the winding current may overshoot the trip level.
In indexer mode, only a rising edge on the STEP pin is needed to move the motor to the next step. The DIR pin sets which direction the motor rotates, by reversing the step sequence. The internal indexer can operate in full-step, half-step, and smaller microsteps up to 1/32-step, depending on the state of the M0 and M1 pins. The M0 and M1 pins can also be connected directly to ground or to VINT to program the step modes, if desired. If the sleep function is not needed, nSLEEP can be connected to VM with an approximate 47-kΩ resistor. Step sequences for full and half step are shown below.
Table 7 lists the design parameters.
PARAMETER | REFERENCE | EXAMPLE VALUE |
---|---|---|
Supply Voltage | VM | 6 V |
Motor Winding Resistance | RL | 3.9 Ω |
Motor Winding Inductance | IL | 2.9 mH |
Motor Full Step Angle | θstep | 1.8°/step |
Target Microstepping Level | nm | 8 µsteps per step |
Target Motor Speed | V | 120 RPM |
Target Full-Scale Current | IFS | 1.25 A |
Phase/enable mode can be used with a simple interface to a controller to operate a stepper motor in full or half step modes. The decay mode can be set by changing the values of the resistors connected to the ADECAY and BDECAY pins. The M1 pin is driven to logic high (by connecting to the VINT supply), to allow a zero-current (off) state when the xENBL pin is set low. Coil current is set by the RSENSE resistors. If the sleep function is not needed, nSLEEP can be connected to VM with an approximate 47-kΩ resistor.
The first step in configuring the DRV8834 requires the desired motor speed and microstepping level. If the target application requires a constant speed, then a square wave with frequency ƒstep must be applied to the STEP pin.
If the target motor start-up speed is too high, the motor will not spin. Make sure that the motor can support the target speed or implement an acceleration profile to bring the motor up to speed.
For a desired motor speed (v), microstepping level (nm), and motor full step angle (θstep),
θstep can be found in the stepper motor data sheet or written on the motor itself.
For the DRV8834, the microstepping level is set by the MODE pins and can be any of the settings in Table 6. Higher microstepping will mean a smoother motor motion and less audible noise, but will increase switching losses and require a higher fstep to achieve the same motor speed.
In a stepper motor, the set full-scale current (IFS) is the maximum current driven through either winding. This quantity will depend on the xVREF analog voltage and the sense resistor value (RSENSE). During stepping, IFS defines the current chopping threshold (ITRIP) for the maximum current step. The gain of DRV8834 is set for 5 V/V.
To achieve IFS = 1.25 A with RSENSE of 0.2 Ω, xVREF should be 1.25 V.
The DRV8834 supports three different decay modes: slow decay, fast decay, and mixed decay. The current through the motor windings is regulated using a fixed-frequency PWM scheme. This means that after any drive phase, when a motor winding current has hit the current chopping threshold (ITRIP), the DRV8834 will place the winding in one of the three decay modes until the PWM cycle has expired. Afterward, a new drive phase starts.
The blanking time TBLANK defines the minimum drive time for the current chopping. ITRIP is ignored during TBLANK, so the winding current may overshoot the trip level.
Table 8 lists the design parameters.
PARAMETER | REFERENCE | EXAMPLE VALUE |
---|---|---|
Supply voltage | VM | 6 V |
Motor winding resistance | RL | 3.9 Ω |
Motor winding inductance | IL | 2.9 mH |
Motor full step angle | θstep | 1.8°/step |
Target microstepping level | nm | 128 µsteps per step |
Target motor speed | V | 120 RPM |
Target full-scale current | IFS | 1.25 A |
Using a microcontroller with two DAC outputs, very high resolution microstepping can be performed with the DRV8834. In this mode, the coil current direction is controlled by the PHASE pins, and the current in each coil is independently set using the two VREF input pins, which are connected to DACs. In addition, the microcontroller can set the decay mode for each coil dynamically, by driving the xDECAY pin low for slow decay, high for fast decay, or high-impedance which sets mixed decay (based on the value of a resistor connected to ground). If the sleep function is not needed, nSLEEP can be connected to VM with an approximate 47-kΩ resistor.
For more details on this technique, refer to TI Application Report, High Resolution Microstepping Driver With the DRV88xx Series (SLVA416).