TPS43330A-Q1 Low IQ, Single-Boost Dual Synchronous Buck Controller

Table 1. Output Voltage Settings

Table 2. Mode Control

7.4.1.1 Frequency Selection and External Synchronization

The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending upon the resistor value at the RT pin. A short-circuit to ground or a high impedance (open) at this pin sets the default switching frequency to 400 kHz. Using a resistor at RT, set another frequency according to Equation 1.

Equation 1.

For example,

600 kHz requires 40 kΩ

150 kHz requires 160 kΩ

Synchronizing to an external clock at the SYNC pin in the same frequency range of 150 kHz to 600 kHz is also possible. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the specified range. The device also detects a loss of clock at this pin, and on detection of this condition, the device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies, 180 degrees out-of-phase.

7.4.1.2 Enable Inputs

Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins, with a threshold of 1.7 V for the high level, and with which direct connection to the battery is permissible for self-bias. The low threshold is 0.7 V. These pins have internal pullup currents of 0.5 µA (typical). As a result, an open circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device shuts down and consumes a current of less than 4 µA.

7.4.1.3 Feedback Inputs

The resistor-feedback divider network connected to the FBx (feedback) pins sets the output voltage. Choose this network such that the regulated voltage at the FBx pin equals 0.8 V. The FBx pins have a 100-nA pullup current source as a protection feature in case the pins open up as a result of physical damage.

7.4.1.4 Soft-Start Inputs

In order to avoid large inrush currents, each buck controller has an independent programmable soft-start timer. The voltage at the SSx pin acts as the soft-start reference voltage. The 1-µA pullup current available at the SSx pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After start-up, the pullup current ensures that SSx is higher than the internal reference of 0.8 V; 0.8 V then becomes the reference for the buck controllers. Equation 2 calculates the soft-start ramp time:

Equation 2.

where

• I_SS = 50 µA (typical)
• ∆V = 0.8 V
• C_SS is the required capacitor for ∆t, the desired soft-start time

An alternative use of the soft-start pins is as tracking inputs. In this case, connect them to the supply to be tracked through a suitable resistor-divider network.

7.4.1.5 Current-Mode Operation

Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at the set value. The error between the feedback voltage at FBx and the internal reference produces a signal at the output of the error amplifier (COMPx) which serves as the target for the peak inductor current. The device senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares voltage with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at FBx, causing V_COMPx to fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. This process maintains the output voltage in regulation.

The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current reaches the peak value. Once this MOSFET turns off, and after a small delay (shoot-through delay) the lower N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the bootstrap capacitor at CBx, which allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck regulator switches at one-fourth of the normal frequency.

7.4.1.6 Current Sensing and Current Limit With Foldback

Clamping of the maximum value of COMPx limits the maximum current through the inductor to a specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus providing current foldback protection, which protects the high-side external MOSFET from excess current (forward-direction current limit).

Similarly, if a fault condition shorts the output to a high voltage and the low-side MOSFET turns fully on, the COMPx node drops low. A clamp is on the lower end as well in order to limit the maximum current in the low-side MOSFET (reverse-direction current limit).

An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum forward peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified value is for low duty cycles only. At typical duty-cycle conditions around 40% (assuming 5-V output and 12-V input),
50 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics (see Figure 17) provide a guide for using the correct current-limit sense voltage.

The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range, thus allowing DCR current-sensing using the DC resistance of the inductor for higher efficiency. Figure 23 shows DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance. Hence, using the more-accurate sense resistor for current sensing is advantageous.

Figure 23. DCR Sensing Configuration

7.4.1.7 Slope Compensation

Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable operation under all conditions. For optimal performance of this circuit, choose the inductor and sense resistor according to the following:

Equation 3.

where

• L is the buck-regulator inductor in henry
• R_S is the sense resistor in ohms
• f_sw is the buck-regulator switching frequency in hertz

7.4.1.8 Power-Good Outputs and Filter Delays

Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx pins and indicating whether the output voltage falls below a specified power-good threshold. This threshold has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-drain output at the PGx pins. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the pullup resistor to a rail other than the output of that particular buck channel causes a constant-current flow through the resistor when the buck controller is powered down.

In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to the set value after a long negative transient, assertion of the power-good indicator (release of the open-drain pin) occurs after the same delay. Use of this delay pauses the release of the reset. Program the duration of the delay by using a suitable capacitor at the DLYAB pin according to Equation 4.

Equation 4.

When the DLYAB pin is open, the delay setting is for a default value of 20 µs typical. The power-good delay timing is common to both the buck rails, but the power-good comparators and indicators function independently.

7.4.1.9 Light-Load PFM Mode

An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. An open or low on the SYNC pin allows the buck controllers to operate in discontinuous mode at light loads by turning off the low-side MOSFET on detection of a zero-crossing in the inductor current.

In discontinuous mode, as the load decreases, the duration when both the high-side and low-side MOSFETs turn off increases (deep-discontinuous mode). In case the duration exceeds 60% of the clock period and V_BAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this switching typically occurs at 1% of the set full-load current if the choice of the inductor and sense resistor is as recommended in Slope Compensation.

In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8-V internal reference. Whenever the FBx value falls below the reference, the high-side MOSFET turns on for a pulse duration inversely proportional to the difference VIN – Sx2. At the end of this on-time, the high-side MOSFET turns off and the current in the inductor decays until the current becomes zero. The low-side MOSFET does not turn on. The next pulse occurs the next time FBx falls below the reference value. This pulsing results in a constant volt-second t_on hysteretic operation with a total device-quiescent current consumption of 30 µA when a single-buck channel is active and of 35 µA when both channels are active.

As the load increases, the pulses become more and more frequent and move closer to each other until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion to exit the low-power mode is when V_IN falls low enough to require higher than 80% duty cycle of the high-side MOSFET.

The TPS43330A-Q1 supports the full-current load during low-power mode until the transition to normal mode takes place. The design ensures that exit of the low-power mode occurs at 10% (typical) of full-load current if the selection of the inductor and sense resistor is as recommended. Moreover, a hysteresis always exists between the entry and exit thresholds to avoid oscillating between the two modes.

In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for low-power mode entry. With the boost controller enabled, low-power mode is possible only if V_BAT is high enough to prevent the boost from switching and if DIV is open or set to GND. A high (V_REG) level on DIV inhibits low-power mode, unless ENC is set to low.

Table 4. Application Example

8.2.2.1 Boost Component Selection

A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in its transfer function. The RHP zero relates inversely to the load current and inductor value and directly to the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the bandwidth is too close to the RHP zero frequency, the regulator becomes unstable.

Thus, for high-power systems with low input voltages, choose a low inductor value. A low value increases the amplitude of the ripple currents in the N-channel MOSFET, the inductor, and the capacitors for the boost regulator. Select these components with the ripple-to-RHP zero trade-off in mind and considering the power dissipation effects in the components due to parasitic series resistance.

A boost converter that operates always in the discontinuous mode does not contain the RHP zero in the transfer function. However, designing for the discontinuous mode demands an even lower inductor value that has high ripple currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, it becomes unstable.

Figure 25. Boost Compensation Components

8.2.2.2 Boost Maximum Input Current I_{IN_MAX}

The maximum input current flows at the minimum input voltage and maximum load. The efficiency for V_BAT = 5 V at 2.5 A is 80%, based on Figure 7.

Equation 5.

Hence,

Equation 6.

8.2.2.3 Boost Inductor Selection, L

Allow input ripple current of 40% of I_{IN max} at V_BAT = 5 V.

Equation 7.

Choose a lower value of 4 µH in order to ensure a high RHP-zero frequency while making a compromise that expects a high current ripple. This inductor selection also makes the boost converter operate in discontinuous conduction mode, where it is easier to compensate.

The inductor-saturation current must be higher than the peak-inductor current and some percentage higher than the maximum current-limit value set by the external resistive-sensing element.

Determine the saturation rating at the minimum input voltage, maximum output current, and maximum core temperature for the application.

8.2.2.4 Inductor Ripple Current, I_RIPPLE

Based on an inductor value of 4 µH, the ripple current is approximately 3.1 A.

8.2.2.5 Peak Current in Low-Side FET, I_PEAK

Equation 8.

Based on this peak current value, calculate the external current-sense resistor R_SENSE.

Equation 9.

Select 20 mΩ, allowing for tolerance.

The filter component values R_IFLT and C_IFLT for current sense are 1.5 kΩ and 1 nF, respectively, which allows for good noise immunity.

8.2.2.6 Right Half-Plane Zero RHP Frequency, f_RHP

Equation 10.

8.2.2.7 Output Capacitor, C_OUTx

To ensure stability, choose output capacitor C_OUTx such that

Equation 11.

Select C_OUTx = 680 µF.

This capacitor is usually aluminum electrolytic with ESR in the tens-of-milliohms. ESR in this range is good for loop stability, because it provides a phase boost. The output filter components, L and C, create a double pole (180-degree phase shift) at a frequency f_LC and the ESR of the output capacitor R_ESR creates a zero for the modulator at frequency f_ESR. One can determine these frequencies by Equation 12.

Equation 12.

This satisfies f_LC ≤ 0.1 f_RHP.

Potentially use a parallel configuration of smaller values to achieve this R_ESR or recalculate with the correct value.

8.2.2.8 Bandwidth of Boost Converter, f_C

Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between stability and transient response:

f_LC < f_ESR< f_C< f_{RHP Zero}

f_C < f_{RHP Zero} / 3

f_C < f_SW / 6

f_LC < f_C / 3

8.2.2.9 Output Ripple Voltage Due to Load Transients, ∆V_OUTx

Assume a bandwidth of f_C = 10 kHz.

Equation 13.

Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters are high-voltage tolerant, a higher excursion on the boost output is tolerable in some cases. In such cases, choose smaller components for the boost output.

8.2.2.10 Selection of Components for Type II Compensation

The required loop gain for unity-gain bandwidth (UGB) is

Equation 14.

The boost-converter error amplifier (OTA) has a Gm that is proportional to the V_BAT voltage, which allows a constant loop response across the input-voltage range and makes compensation easier by removing the dependency on V_BAT.

Equation 15.

8.2.2.11 Input Capacitor, C_IN

The input ripple required is lower than 50 mV.

Equation 16.

Therefore, TI recommends 220 µF with 10-mΩ ESR or a parallel configuration of several capacitors to achieve such ESR-levels.

8.2.2.12 Output Schottky Diode D1 Selection

Maximizing efficiency requires a Schottky diode with low forward-conducting voltage (V_F) over temperature and fast switching characteristics. The reverse breakdown voltage must be higher than the maximum input voltage, and the component must have low reverse leakage current. Additionally, the peak forward current must be higher than the peak inductor current. Equation 17 gives the power dissipation in the Schottky diode:

Equation 17.

8.2.2.13 Low-Side MOSFET (BOT_SW3)

Equation 18.

The times t_r and t_f denote the rising and falling times of the switching node and relate to the gate-driver strength of the TPS43330A-Q1 and gate Miller capacitance of the MOSFET. The first term, t_r, denotes the conduction losses, which the low ON-resistance of the MOSFET minimizes. The second term, t_f, denotes the transition losses which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. Transition losses are higher at high output currents and low input voltages (due to the large input peak current), and when the switching time is low.

8.2.2.14 BuckA Component Selection

8.2.2.14.1 BuckA Component Selection

Equation 19.

t_{ON min} is higher than the minimum duty cycle specified (100 ns typical). Hence, the minimum duty cycle is achievable at this frequency.

8.2.2.14.2 Current-Sense Resistor R_SENSE

Based on the typical characteristics for the V_SENSE limit with V_IN versus duty cycle, the sense limit is approximately 65 mV (at V_IN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose a V_SENSE maximum of 50 mV.

Equation 20.

Select 15 mΩ.

8.2.2.15 Inductor Selection L

As explained in the description of the buck controllers, for optimal slope compensation and loop response, choose the inductor such that:

Equation 21.

where

• K_FLR = coil-selection constant = 200

Choose a standard value of 8.2 µH. For the buck converter, choose the inductor saturation currents and core to sustain the maximum currents.

8.2.2.16 Inductor Ripple Current I_RIPPLE

At the nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of I_{OUT max} ≈ 1 A.

8.2.2.17 Output Capacitor C_OUTA

Select an output capacitance C_OUTA of 100 µF with low ESR in the range of 10 mΩ, giving ∆V_OUT(Ripple) ≈ 15 mV and a ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within the required limits.

Equation 22.

Equation 23.

Equation 24.

8.2.2.18 Bandwidth of Buck Converter f_C

Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between stability and transient response.

• Crossover frequency f_C between f_SW / 6 and f_SW / 10. Assume f_C = 50 kHz.
• Select the zero f_z ≈ f_C / 10
• Make the second pole f_P2 ≈ f_SW / 2

8.2.2.19 Selection of Components for Type II Compensation

Figure 26. Buck Compensation Components

Equation 25.

where

• V_OUT = 5 V
• C_OUT = 100 µF
• Gm_BUCK = 1 mS
• V_REF = 0.8 V
• K_CFB = 0.125 / R_SENSE = 8.33 S (0.125 is an internal constant)

Use the standard value of R3 = 24 kΩ.

Equation 26.

Use the standard value of 1.5 nF.

Equation 27.

The resulting bandwidth of buck converter f_C

Equation 28.

f_C is close to the target bandwidth of 50 kHz.

The resulting zero frequency f_Z1

Equation 29.

f_Z1 is close to the f_C / 10 guideline of 5 kHz.

The second pole frequency f_P2

Equation 30.

f_P2 is close to the f_SW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.

8.2.2.20 Resistor Divider Selection for Setting V_OUTA Voltage

Equation 31.

Choose the divider current through R1 and R2 to be 50 µA. Then

Equation 32.

and

Equation 33.

Therefore, R2 = 16 kΩ and R1 = 84 kΩ.

8.2.2.21 BuckB Component Selection

Using the same method as for V_BuckA produces the following parameters and components.

Equation 34.

This result is higher than the minimum duty cycle specified (100 ns typical).

Equation 35.

∆I_ripple current ≈ 0.4 A (approximately 20% of I_{OUT max})

Select an output capacitance C_OUTB of 100 µF with low ESR in the range of 10 mΩ.

Assume f_C = 50 kHz.

Equation 36.

Equation 37.

Equation 38.

Equation 39.

Use the standard value of R3 = 30 kΩ.

Equation 40.

Equation 41.

Equation 42.

f_C is close to the target bandwidth of 50 kHz.

The resulting zero frequency f_Z1

Equation 43.

f_Z1 is close to the f_C guideline of 5 kHz.

The second pole frequency f_P2

Equation 44.

f_P2 is close to the f_SW / 2 guideline of 200 kHz.

Hence, the design satisfies all requirements for a good loop.

8.2.2.22 Resistor Divider Selection for Setting V_OUT Voltage

Equation 45.

Choose the divider current through R1 and R2 to be 50 µA. Then

Equation 46.

and

Equation 47.

Therefore, R2 = 16 kΩ and R1 = 50 kΩ.

8.2.2.23 BuckX High-Side and Low-Side N-Channel MOSFETs

An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for these MOSFETs. The output is a totem pole, allowing full-voltage drive of V_REG to the gate with peak output current of 1.5 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the reference for the low-side MOSFET is the power-ground (PGNDx) terminal. For a particular application, select these MOSFETs with consideration for the following parameters: r_DS(on), gate charge Qg, drain-to-source breakdown voltage BVDSS, maximum DC current IDC(max), and thermal resistance for the package.

The times t_r and t_f denote the rising and falling times of the switching node and have a relationship to the gate-driver strength of the TPS43330A-Q1 and to the gate Miller capacitance of the MOSFET. The first term, t_r, denotes the conduction losses, which are minimimal when the ON-resistance of the MOSFET is low. The second term, t_f, denotes the transition losses, which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. Transition losses are lower at low currents and when the switching time is low.

Equation 48.

Equation 49.

In addition, during the dead time (t_d) when both the MOSFETs are off, the body diode of the low-side MOSFET conducts, increasing the losses. The second term in Equation 49 denotes this dead time. Using external Schottky diodes in parallel with the low-side MOSFETs of the buck converters helps to reduce this loss.

Table 5. Application Example 1

Table 6. Application Example 1 – Component Proposals

Table 7. Application Example 2

Table 8. Application Example 2 – Component Proposals