The TPS7A4501-SP is a low-dropout (LDO) regulator optimized for fast-transient response. The 5962-1222402VHA can supply 750 mA of output current with a dropout voltage of 300 mV. The 5962R1222403VXC can supply 1.5 A of output current with a dropout voltage of 320 mV. Quiescent current is well controlled; it does not rise in dropout, as with many other regulators. In addition to fast transient response, the TPS7A4501-SP regulator has very-low output noise, which makes it ideal for sensitive RF supply applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A4501-SP | CFP [U] (10) | 6.35 mm × 6.35 mm |
CFP [HKU] (10) | 7.02 mm × 6.86 mm | |
KGD | N/A(2) |
SPACE
Changes from C Revision (October 2014) to D Revision
Changes from B Revision (October 2014) to C Revision
Changes from A Revision (January 2014) to B Revision
Changes from * Revision (December 2013) to A Revision
Output voltage range is from 1.21 to 20 V. The TPS7A4501-SP is stable with output capacitance as low as 10 μF. Small ceramic capacitors can be used without the necessary addition of ESR, as is common with other regulators. Internal protection circuitry includes reverse-battery protection, current limiting, thermal limiting, and reverse-current protection. The device is available as an adjustable device with a 1.21-V reference voltage. The 5962-1222402VHA is available in 10-pin CFP (U) package and 5962R1222403VXC is available in thermally-enhanced 10-pin CFP (HKU) package. Known good die (KGD) option is available for both 5962-1222402V9A for non-RHA version and 5962R1222403V9A for RHA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
SHDN | 1 | I | Shutdown. SHDN is used to put the TPS7A4501 regulator into a low-power shutdown state. The output is off when SHDN is pulled low. SHDN can be driven by 5-V logic, 3-V logic, or open-collector logic with a pullup resistor. The pullup resistor is required to supply the pullup current of the open-collector gate, normally several microamperes, and SHDN current, typically 3 μA. If unused, the user must connect SHDN to VIN. The device is in the low-power shutdown state if SHDN is not connected. |
IN | 2 | I | Input. Power is supplied to the device through IN. A bypass capacitor is required on this pin if the device is more than six inches away from the main input filter capacitor. In general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. A bypass capacitor (ceramic) in the range of 1 to 10 μF is sufficient. The TPS7A4501 regulator is designed to withstand reverse voltages on IN with respect to ground and on OUT. In the case of a reverse input, which can happen if a battery is plugged in backwards, the device functions as if there is a diode in series with its input. No reverse current flows into the regulator, and no reverse voltage appears at the load. The device protects both itself and the load. |
3 | |||
4 | |||
NC | 5 | NC | This pin is not connected to any internal circuitry. It can be left floating or tied to VIN or GND. |
OUT | 6 | O | Output. The output supplies power to the load. To prevent oscillations, use a minimum output capacitor (ceramic) of 10 μF. Applications with large transient loads to limit peak voltage transients require larger output capacitors. |
7 | |||
8 | |||
ADJ | 9 | I | Adjust. This is the input to the error amplifier. ADJ is internally clamped to ±7 V. It has a bias current of 3 μA that flows into the pin. ADJ voltage is 1.21 V referenced to ground, and the output voltage range is 1.21 to 20 V. |
GND | 10 | — | Ground |
Thermal Vias(1) | — | — | The exposed thermal vias of the HKU package should be connected to a wide ground plane for effective heat dissipation. Refer to Figure 30 and Figure 31 for the typical footprint of the HKU package. |
DIE THICKNESS | BACKSIDE FINISH | BACKSIDE POTENTIAL | BOND PAD METALLIZATION COMPOSITION |
BOND PAD THICKNESS |
---|---|---|---|---|
15 mils | Silicon with backgrind | Floating | TiW/AlCu2 | 1627 nm |
DESCRIPTION | PAD NUMBER | X MIN | Y MIN | X MAX | Y MAX |
---|---|---|---|---|---|
SHDN | 1 | 1729.25 | 55.5 | 1879.25 | 205.5 |
IN | 2 | 1037.25 | 875 | 1187.25 | 1025 |
IN | 3 | 1460.75 | 1255.5 | 1610.75 | 1405.5 |
IN | 4 | 1037.75 | 1384.5 | 1187.75 | 1534.5 |
OUT | 5 | 774.25 | 1634.75 | 924.25 | 1784.75 |
OUT | 6 | 675.25 | 1166 | 825.25 | 1316 |
OUT | 7 | 345.5 | 1299.25 | 495.5 | 1449.25 |
SENSE/ADJ | 8 | 55.5 | 213 | 205.5 | 363 |
GND | 9 | 244 | 17.5 | 394 | 167.5 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VIN | Input voltage | IN | –22 | 22 | V |
OUT | –22 | 22 | |||
Input-to-output differential(2) | –22 | 22 | |||
ADJ | –7 | 7 | |||
SHDN | –22 | 22 | |||
Tlead | Maximum lead temperature (10-s soldering time) | 260 | °C | ||
TJ | Maximum operating junction temperature | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | 4000 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
TJ | Operating junction temperature | –55 | 125 | °C |
THERMAL METRIC(1) | TPS7A4501-SP | UNIT | ||
---|---|---|---|---|
U (CFP) | HKU (CFP) | |||
10 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 86.6 | 51.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance(2) | 10.3 | 6.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 35.6 | 31.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 31.7 | 5.42 | °C/W |
ψJB | Junction-to-board characterization parameter | 53.5 | 31 | °C/W |
PARAMETER | TEST CONDITIONS | TJ | MIN | TYP(9) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
VIN | Minimum input voltage(1)(2) | ILOAD = 500 mA | 25°C | 1.9 | 2.3 | V | ||
ILOAD = 750 mA | Full range | 2.1 | 2.5 | |||||
VADJ | ADJ pin voltage(1)(3) | VIN = 2.21 V, ILOAD = 1 mA | 25°C | 1.196 | 1.21 | 1.224 | V | |
VIN = 2.5 to 20 V, ILOAD = 1 to 750 mA | Full range | 1.174 | 1.21 | 1.246 | ||||
Line regulation(1) | ΔVIN = 2.21 to 20 V, ILOAD = 1 mA |
Full range | 1.5 | 4.5 | mV | |||
Load regulation(1) | VIN = 2.5 V, ΔILOAD = 1 to 750 mA | 25°C | 2 | 8 | mV | |||
Full range | 18 | |||||||
VDO | Dropout voltage (VOUT = 2.4 V) (5)(4)
|
ILOAD = 1 mA | 25°C | 0.02 | 0.05 | V | ||
Full range | 0.07 | |||||||
ILOAD = 100 mA | 25°C | 0.085 | 0.10 | |||||
Full range | 0.13 | |||||||
ILOAD = 500 mA | 25°C | 0.17 | 0.21 | |||||
Full range | 0.27 | |||||||
ILOAD = 750 mA | 25°C | 0.20 | 0.27 | |||||
Full range | 0.33 | |||||||
IGND | GND pin current(4)(6)
VIN = 2.5 V |
ILOAD = 0 mA, | Full range | 1 | 1.5 | mA | ||
ILOAD = 1 mA | Full range | 1.1 | 1.6 | |||||
ILOAD = 100 mA | Full range | 3.3 | 7 | |||||
ILOAD = 500 mA | Full range | 15 | 30 | |||||
ILOAD = 750 mA | Full range | 28 | 45 | |||||
eN(11) | Output voltage noise | COUT = 22 μF, ILOAD = 750 mA, VIN = 7 V, VOUT= 5 V BW = 10 Hz to 100 kHz |
25°C | 50 | μVRMS | |||
IADJ | ADJ pin bias current(1)(7) | 25°C | 3 | 7 | μA | |||
Shutdown threshold | VOUT = OFF to ON | Full range | 0.9 | 2 | V | |||
VOUT = ON to OFF | Full range | 0.15 | 0.75 | |||||
ISHDN | SHDN pin current | VSHDN = 0 V | 25°C | 0.01 | 1 | μA | ||
VSHDN = 20 V | 25°C | 3 | 20 | |||||
Quiescent current in shutdown | VIN = 6 V, VSHDN = 0 V | 25°C | 0.01 | 1 | μA | |||
Ripple rejection(10) | VIN – VOUT = 1.5 V (avg), VRIPPLE = 0.5 VP-P, ƒRIPPLE = 120 Hz, ILOAD = 0.75 A |
25°C | 60 | 68 | dB | |||
ILIMIT | Current limit(10) | VIN = 7 V, VOUT = 0 V | 25°C | 1.7 | 1.9 | A | ||
VIN = 2.5 V | Full range | 1.6 | 1.9 | |||||
IIL | Input reverse leakage current | VIN = –20 V, VOUT = 0 V | Full range | 300 | μA | |||
IRO | Reverse output current(8) | VOUT = 1.21 V, VIN < 1.21 V | 25°C | 300 | 500 | μA | ||
TSD | Thermal shutdown temperature | 175 | °C |
PARAMETER | TEST CONDITIONS | TJ | MIN | TYP(10) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
VIN | Minimum input voltage(1)(2) | ILOAD = 1.5 A | Full range | 2.1 | 2.9 | V | ||
VADJ | ADJ pin voltage(1)(3) | VIN = 2.9 to 20 V, ILOAD = 1 mA to 1.5 A | Full range | 1.174 | 1.21 | 1.246 | V | |
Line regulation(1) | ΔVIN = 2.9 to 20 V, ILOAD = 1 mA | Full range | 2.5 | 6.5 | mV | |||
Load regulation(1) | VIN = 2.9 V, ΔILOAD = 1 mA to 1.5 A | 25°C | 2 | 10 | mV | |||
Full range | 18 | |||||||
VDO | Dropout voltage (VOUT = 19.3 V )(6)(5)
|
ILOAD = 1 mA | 25°C | 0.08 | 0.32 | V | ||
Full range | 0.40 | |||||||
ILOAD = 100 mA | 25°C | 0.14 | 0.40 | |||||
Full range | 0.58 | |||||||
ILOAD = 500 mA | 25°C | 0.25 | 0.40 | |||||
Full range | 0.60 | |||||||
ILOAD = 750 mA | 25°C | 0.30 | 0.40 | |||||
Full range | 0.62 | |||||||
ILOAD = 1 A | 25°C | 0.34 | 0.45 | |||||
Full range | 0.65 | |||||||
ILOAD = 1.25 A | 25°C | 0.40 | 0.50 | |||||
Full range | 0.68 | |||||||
ILOAD = 1.5 A | 25°C | 0.45 | 0.60 | |||||
Full range | 0.75 | |||||||
IGND | GND pin current(4)(7)
VIN = 2.9 V |
ILOAD = 0 mA | Full range | 1 | 1.5 | mA | ||
ILOAD = 1 mA | Full range | 1.1 | 1.6 | |||||
ILOAD = 100 mA | Full range | 3.3 | 7 | |||||
ILOAD = 500 mA | Full range | 8.5 | 30 | |||||
ILOAD = 750 mA | Full range | 15 | 45 | |||||
ILOAD = 1 A | Full range | 25 | 50 | |||||
ILOAD = 1.25 A | Full range | 36 | 80 | |||||
ILOAD = 1.5 A | Full range | 53 | 105 | |||||
eN(13) | Output voltage noise | COUT = 22 μF, ILOAD = 1.5 A, VIN = 5.5 V, VOUT = 5 V BW = 10 Hz to 100 kHz |
25°C | 50 | μVRMS | |||
IADJ | ADJ pin bias current(1)(8) | 25°C | 3 | 7 | μA | |||
Full range | 5.5 | 15 | ||||||
Shutdown threshold | VOUT = OFF to ON | Full range | 0.9 | 2 | V | |||
VOUT = ON to OFF | Full range | 0.15 | 0.75 | |||||
ISHDN | SHDN pin current | VSHDN = 0 V | Full range | 0.01 | 1 | μA | ||
VSHDN = 20 V | Full range | 3 | 20 | |||||
Quiescent current in shutdown | VIN = 6 V, VSHDN = 0 V | Full range | 0.01 | 10 | μA | |||
VIN = 6 V, VSHDN = 0 V, Post 100kRads (si), TJ = 25°C(11) | 25°C | 15 | 50 | |||||
Ripple rejection(12) | VIN – VOUT = 1.5 V (avg), VRIPPLE = 0.5 VP-P, ƒRIPPLE = 120 Hz, ILOAD = 0.75 A |
25°C | 60 | 68 | dB | |||
Full range | 58 | 63 | ||||||
VIN – VOUT = 1.5 V (avg), VRIPPLE = 0.5 VP-P, fRIPPLE = 120 Hz, ILOAD = 1.5 A |
25°C | 50 | 60 | |||||
Full range | 44 | 52 | ||||||
ILIMIT | Current limit(12) | VIN = 7 V, VOUT = 0 V | Full range | 1.7 | 1.9 | A | ||
VIN = 2.9 V | Full range | 1.6 | 1.9 | |||||
IIL | Input reverse leakage current | VIN = –20 V, VOUT = 0 V | Full range | 300 | μA | |||
IRO | Reverse output current(9) | VOUT = 1.21 V, VIN < 1.21 V | Full range | 300 | 500 | μA | ||
TSD | Thermal shutdown temperature | 175 | °C |
VIN = 6 V | IOUT = 0 A | VSHDN = VIN |
TJ = 25°C | ROUT = 4.3 kΩ | VSHDN = VIN |
TJ = 25°C | VSHDN = VIN | VOUT = 1.21 V |
VSHDN = 0 V |
IOUT = 1 mA |
VIN = 7 V | VOUT = 0 V | |
VIN = 0 V | VOUT = 1.21 V | |
IOUT = 750 mA | ||||
VOUT = 2.4 V |
IOUT = 1 mA | VIN = 2.9 V |
TJ = 25°C | VSHDN = VIN | |
VOUT = 1.21 V |
VIN = VOUT(nom) + 1 |
IOUT = 1 mA |
ΔVOUT = 100 mV |
TJ = 25°C | VIN = 0 V | VOUT = VADJ |
Current flows into OUT pin |
VIN = 2.7 V | CIN = 0 | COUT = 10 µF |
(ceramic) | ||
IOUT = 750 mA | VRipple = 0.05 VPP | TA = 25°C |
The TPS7A4501-SP is a 1.5-A LDO regulator optimized for fast-transient response. The devices are capable of supplying 1.5 A at a dropout voltage of 320 mV. The low operating quiescent current (1 mA) drops to less than 50 μA in shutdown. In addition to the low quiescent current, the TPS7A4501-SP regulators incorporate several protection features that make them ideal for use in battery-powered systems. The devices are protected against both reverse input and reverse output voltages. In battery-backup applications where the output can be held up by a backup battery when the input is pulled to ground, the TPS7A4501-SP functions as if it has a diode in series with its output and prevents reverse current flow. Additionally, in dual-supply applications where the regulator load is returned to a negative supply, the output can be pulled below ground by as much as (20 V – VIN) and still allow the device to start and operate.
The adjustable TPS7A4501-SP has an output voltage range of 1.21 to 20 V. The output voltage is set by the ratio of two external resistors as shown in Figure 20. The device maintains the voltage at the ADJ pin at 1.21 V referenced to ground. The current in R1 is then equal to (1.21 V/R1), and the current in R2 is the current in R1 plus the ADJ pin bias current. The ADJ pin bias current, 3 μA at 25°C, flows through R2 into the ADJ pin. Calculate the output voltage using the formula shown in Figure 20. The value of R1 should be less than 4.17 kΩ to minimize errors in the output voltage caused by the ADJ pin bias current. Note that in shutdown, the output is turned off, and the divider current is zero.
The adjustable device is tested and specified with the ADJ pin tied to the OUT pin for an output voltage of 1.21 V. Specifications for output voltages greater than 1.21 V are proportional to the ratio of the desired output voltage to 1.21 V: VOUT / 1.21 V. For example, load regulation for an output current change of 1 mA to 1.5 A is –3 mV (typical) at VOUT = 1.21 V. At VOUT = 5 V, load regulation is:
The TPS7A4501-SP can be used in a fixed-voltage configuration. Connect the SENSE/ADJ pin to OUT for proper operation. Figure 21 shows an example of this for a fixed output voltage of 1.21 V. During fixed voltage operation, the SENSE/ADJ pin can be used for a Kelvin connection if routed separately to the load. This allows the regulator to compensate for voltage drop across parasitic resistances (RP) between the output and the load. This compensation becomes more crucial with higher-load currents.
Like many IC power regulators, the TPS7A4501-SP has safe operating area protection. The safe area protection decreases the current limit as input-to-output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. The protection is designed to provide some output current at all values of input-to-output voltage up to the device breakdown.
When power is first turned on, as the input voltage rises, the output follows the input, allowing the regulator to start up into very-heavy loads. During start up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. With a high input voltage, a problem can occur wherein removal of an output short does not allow the output voltage to recover. Other regulators also exhibit this phenomenon, so it is not unique to the TPS7A4501-SP.
The problem occurs with a heavy output load when the input voltage is high and the output voltage is low. Common situations occur immediately after the removal of a short circuit or when the shutdown pin is pulled high after the input voltage has already been turned on. The load line for such a load may intersect the output current curve at two points. If this happens, there are two stable output operating points for the regulator. With this double intersection, the input power supply may need to be cycled down to 0 and brought up again to make the output recover.
The TPS7A4501-SP regulator is designed to provide low output voltage noise over the 10-Hz to 100-kHz bandwidth while operating at full load. Output voltage noise is typically 50 µV/√Hz over this frequency bandwidth for the TPS7A4501-SP. For higher output voltages (generated by using a resistor divider), the output voltage noise is gained up accordingly.
Higher values of output voltage noise may be measured when care is not exercised with regard to circuit layout and testing. Crosstalk from nearby traces can induce unwanted noise onto the output of the TPS7A4501-SP. The user must also consider power-supply ripple rejection; the TPS7A4501-SP regulator does not have unlimited power-supply rejection and passes a small portion of the input noise through to the output.
The TPS7A4501-SP regulator incorporates several protection features, which makes the regulator ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device is protected against reverse input voltages, reverse output voltages, and reverse voltages from output to input.
Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation, the junction temperature should not exceed 125°C. TPS7A4501-SP incorporates thermal protection which disables the output when the junction temperature rises approximately 175°C, allowing the device to cool.
The input of the device withstands reverse voltages of 20 V. Current flow into the device is limited to less than 1 mA (typically less than 100 μA), and no negative voltage appears at the output. The device protects both itself and the load. This provides protection against batteries that can be plugged in backward.
The output of the TPS7A4501-SP can be pulled below ground without damaging the device. If the input is left open circuit or grounded, the output can be pulled below ground by 20 V. The output acts like an open circuit; no current flows out of the pin. If the input is powered by a voltage source, the output sources the short-circuit current of the device and protects itself by thermal limiting. In this case, grounding the SHDN pin turns off the device and stops the output from sourcing the short-circuit current.
The ADJ pin of the adjustable device can be pulled above or below ground by as much as 7 V without damaging the device. If the input is left open circuit or grounded, the ADJ pin acts like an open circuit when pulled below ground and like a large resistor (typically 5 kΩ) in series with a diode when pulled above ground.
In situations where the ADJ pin is connected to a resistor divider that would pull the ADJ pin above its 7-V clamp voltage if the output is pulled high, the ADJ pin input current must be limited to less than 5 mA. For example, a resistor divider is used to provide a regulated 1.5-V output from the 1.21-V reference when the output is forced to 20 V. Choose the top resistor of the resistor divider so as to limit the current into the ADJ pin to <5 mA when the ADJ pin is at 7 V. The 13-V difference between OUT and ADJ divided by the 5-mA maximum current into the ADJ pin yields a minimum top resistor value of 2.6 kΩ.
In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage, or is left open circuit.
When the IN pin of the TPS7A4501-SP is forced below the OUT pin or the OUT pin is pulled above the IN pin, input current typically drops to less than 2 μA. This can happen if the input of the device is connected to a discharged (low-voltage) battery and the output is held up by either a backup battery or a second regulator circuit. The state of the SHDN pin has no effect on the reverse output current when the output is pulled above the input.
Table 1 shows the device modes.
SHDN | DEVICE STATE |
---|---|
H | Regulated voltage |
L | Shutdown |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS7A4501-SP regulator has very-low output noise, which makes it ideal for sensitive RF supply applications.
This section highlights some of the design considerations when implementing this device in various applications.
Table 2 shows the design requirements.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage (VIN) | 5 V |
Output voltage (VOUT) | 2.5 V |
Output current (IOUT) | 0 to 1 A |
Load regulation | 1% |
The TPS7A4501-SP has an adjustable output voltage range of 1.21 to 20 V. The output voltage is set by the ratio of two external resistors, R1 and R2, as shown in Figure 23. The device maintains the voltage at the ADJ pin at 1.21 V referenced to ground. The current in R1 is then equal to (1.21 V/R1), and the current in R2 is the current in R1 plus the ADJ pin bias current. The ADJ pin bias current, 3 µA at 25°C, flows through R2 into the ADJ pin. Calculate the output voltage using Equation 2.
The value of R1 should be less than 4.17 kΩ to minimize errors in the output voltage caused by the ADJ pin bias current. Note that in shutdown the output is turned off, and the divider current is zero. For an output voltage of 2.50 V, R1 is set to 4 kΩ. R2 is then found to be 4.22 kΩ using Equation 2.
The adjustable device is tested and specified with the ADJ pin tied to the OUT pin for an output voltage of 1.21 V. Specifications for output voltages greater than 1.21 V are proportional to the ratio of the desired output voltage to 1.21 V: VOUT / 1.21 V. For example, load regulation for an output current change of 1 mA to 1.5 A is –2 mV (typical) at VOUT = 1.21 V. At VOUT = 2.50 V, the typical load regulation is:
shows the actual change in output is about 3 mV for a 1-A load step. The maximum load regulation at 25°C is –8 mV. At VOUT = 2.50 V, the maximum load regulation is:
Because 16.53 mV is only 0.7% of the 2.5-V output voltage, the load regulation meets the design requirements.
The TPS7A4501-SP regulator is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. TI recommends a minimum output capacitor of 10 μF with an ESR of 3 Ω or less to prevent oscillations. Larger values of output capacitance can decrease the peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the TPS7A4501-SP, increase the effective output capacitor value.
Give extra consideration to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. The most common dielectric used for a harsh environment is X7R. Ceramic capacitors lose capacitance when DC bias is applied across the capacitor. This capacitance loss is due to the polarization of the ceramic material. The capacitance loss is not permanent: after a large DC bias is applied, reducing the DC bias reduces the degree of polarization and capacitance increases. DC bias effects vary dramatically with voltage rating, case size, capacitor value, and capacitor manufacturer. Because a capacitor could lose more than 50% of its capacitance with DC bias voltages near the voltage rating of the capacitor, it is important to consider DC bias when selecting a ceramic capacitor for an application.
Ceramic capacitors' dielectric also changes over the temperature range. For example X7R, the first letter X denotes lower temperature range –55°C whereas 7 denotes a higher temperature range 125°C and R denotes capacitance variation over the temperature range (±15%). For harsh environment applications, minimum dielectric thickness must be 1 mil for 100-V DC-rated capacitor and 0.8 mil for 50-V DC-rated capacitors.
Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients.
Tantalum capacitors can provide higher capacitance per unit volume. Tantalum capacitors can be either manganese dioxide (MNO2)-based capacitors where the cathode is MN02 or polymer. MN02-based tantalum capacitors exhibit high ESR as compared to polymer-based tantalum capacitors. MN02-based tantalum capacitors require in excess of 60% voltage derating. Thus, a 10-V rated capacitor can only be used for 3.3-V application. Whereas polymer-based capacitors only require 10% voltage derating. Paralleling ceramic and tantalum capacitors provide optimum balance between capacitance and ESR.
Table 3 highlights some of the capacitors used in the device.
CAPACITOR PART NUMBER | CAPACITOR DETAILS TYPE VENDOR (CAPACITOR, VOLTAGE, ESR) |
TYPE | VENDOR |
---|---|---|---|
T493X226M025AH6x20 | 22 μF, 25 V, 35 mΩ | Tantalum - MnO2 | Kemet |
T525D476M016ATE035 | 47 μF, 10 V, 35 mΩ | Tantalum - Polymer | Kemet |
T525D107M010ATE025 | 100 μF, 10 V, 25 mΩ | Tantalum - Polymer | Kemet |
T541X337M010AH6720 | 330 μF, 10 V, 6 mΩ | Tantalum - Polymer | Kemet |
T525D227M010ATE025 | 220 μF, 10 V, 25 mΩ | Tantalum - Polymer | Kemet |
T495X107K016ATE100 | 100 μF, 16 V, 100 mΩ | Tantalum - MnO2 | Kemet |
CWR29FK227JTHC | 220 μF, 10 V, 180 mΩ | Tantalum - MnO2 | AVX |
THJE107K016AJH | 100 μF, 16 V, 58 mΩ | Tantalum | AVX |
THJE227K010AJH | 220 μF, 10 V, 40 mΩ | Tantalum | AVX |
SR2225X7R335K1P5#M123 | 3.3 μF, 25 V, 10 mΩ | Ceramic | Presidio Components Inc |
TPS7A4501-SP is internally compensated. However, the user can implement a lead network using C3 to boost the phase margin as well as reduce output noise.
R1, the bottom resistor, and R2, the top resistor, form the output voltage divider network. C3 across R2 adds a lead network.
For R1 = 3.2 kΩ and R2 = 10 kΩ, VOUT is set at 5 V and C3 = 470 pF.
Zero and pole can be calculated as shown in the following equations.
The following waveforms indicate the transient behavior of the TPS7A4501-SP.