SLVSE46 Data sheet

SLVSE46A November 2017 – January 2018

PRODUCTION DATA.

7.3.14.2 CLOCK Execute Instruction (CXE) and DATA Execute Instruction (DXE)

This instruction is used to modify the state of the level shifter outputs. C1, C2, C3, C4, C5 and C6 are 2-bit values dedicated to the master high-voltage output clocks GCK1-2, GCK3-4, GCK5, GCK6, GCK7, GCK8, GCK9-10 and GCK11-12. D1, D2 and D3 are 1-bit values used to control GSP1-2, GCP, VSS and GGP1-2 outputs. The coding for each channel is described in its corresponding channel description section above.

High-voltage clock outputs GCK2, CCK4, GCK6, GCK8, GCK10 and GCK12 are not directly controlled by the EXE instruction but trail their respective master channels with a programmable delay equal to an integer number of logic clock cycles as shown in Figure 17. A C1256_SEP setting of 1 delays each slave channel by one logic clock cycle against its preceding channel. A C1256_SEP setting of 2 delays each slave channel by two logic-clock cycles, up to a maximum delay of 255. A C1256_SEP setting of 0 yields no delay, such that the slave output signals are identical, non-shifted copies of the master channel. The clock separation is set in the and registers and the same setting applies to all slave clocks, regardless of their master channel. Note that the master channel must not have more than 4 state transitions within the separation window for the signal to be reproduced properly on a slave output.

The idle count is used to extend the dwell time of an execute instruction. With an idle count of 0, the defined states are applied to the outputs and kept steady for one clock cycle before the sequencer advances to the next instruction. The dwell time may be increased by up to 255 clock cycles by increasing the idle count. The resulting dwell time equals the idle count plus one clock cycle.

Control bits D1 through D3 are dedicated to the control of the GSP1-2, GCP, VSS and GGP1-2 outputs. Different from the C1, C2, C3, C4, C5 and C6 bits, there is no fixed channel assignment, although in a typical use case the channels are used as follows:

D1 controls GSP1, GSP2
D2 is not used or controls GGP1, GGP2
D3 controls GCP, VSS

In most use cases GSP2 and GCP2 level shifter outputs are not directly controlled by D1/D3 control bits but rather by one of the delayed signals, D1A, and D2A. The 8-bit separation settings for D1A and D2A are independently programmable through the and and registers, respectively. Channel assignment is controlled by the registers and the available assignment options are shown in Figure 17. Channel assignment may be dynamically changed during run time by modifying the register settings through a LDR instruction.

D1, D2, and D3 are single bit only. If a channel is assigned to a single-bit control, only the high and low drive options are available. See coding tables under High-Voltage Control Outputs (GSP, GCP, GGP) for details.

The idle count is used to extend the dwell time of an execute instruction.

Figure 18. Clock Separation.