SLVSE46 Data sheet

SLVSE46A November 2017 – January 2018

PRODUCTION DATA.

7.3.14 Programmable Pattern Sequencer

The programmable pattern sequencer governs the level shifter outputs during the frame active and blanking time. It requires only two inputs from the TCON, a line-clock (LN_CLK) and a start pulse (LS_START) that indicates the start of a new frame. The sequencer consists of two main parts, a signal generator that calculates the output state for each analog output, and a channel selector / output gate that determines if the signal is actually applied to the output. The signal generator is explained in detail under Signal Generator Architecture and Instruction Set, output gating under Channel Selection and Output Gating.

Figure 15. High-Level Sequencer Block Diagram.

The information from which the signal generator calculates the output states is stored as a series of consecutive instructions in pattern memory. Pattern memory holds up to 54 instructions (logical address 0 to 53) that can be used to store a single sequence or may be divided into multiple sections containing different sequences. The start address of a sequence is stored in register .

Level shifter operation is gated by the following conditions:

The internal EN_DLY counter must have expired,
LS_CNTRL pin must be high, and
All rails must indicate power-good

Sequence execution starts on the rising edge of LS_START terminates when the END instruction is reached. Detailed start / stop timing is shown in section Preset and START. The signal generator distinguishes between Master and Slave channels. Master channels are controlled directly by the control bits of an CXE instruction. Slave channels follow one of the master channels with a programmable separation count. See CLOCK Execute Instruction (CXE) and DATA Execute Instruction (DXE) for details.

To remain in lock-step with the source-driver data, the sequencer clock (SEQ_CLK) is derived from a reference clock provided by the TCON and connected to the LN_CLK pin. Typically this will be the line clock but can be an integer multiple or fraction of the line clock as long as he frequency is within the valid input frequency range for the PLL.

The pattern sequencer is configured via a set of registers, some of which can be dynamically modified by the sequencer during run time. Registers are addressed by their logical address rather than I²C address and the mapping is shown in Table 1.

Table 1. Logical Address Mapping of Sequencer Configuration Registers.

REGISTER	LOGICAL ADDRESS	SEQUENCER ACCESS
	N/A	READ
	N/A	READ
	N/A	READ
	N/A	READ
	0x0	READ / WRITE
	0x1	READ / WRITE
	0x2	READ / WRITE
	0x3	READ / WRITE
	0x4	READ / WRITE
	0x5	READ / WRITE
	0x6	READ / WRITE
	0x7	READ / WRITE
	0x8	READ / WRITE
	0x9	READ / WRITE
	0xA	READ / WRITE
	0xB	READ / WRITE
	0xC	READ / WRITE
	0xD	READ / WRITE